Renesas ISL23428WFVZ-T7A
- Part No.:
- ISL23428WFVZ-T7A
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ISL23428WFVZ-T7A.pdf
- Description:
- IC DGT POT 10KOHM 128TAP 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL23428WFVZ-T7A from Renesas (formerly Intersil) is a dual, volatile, 128-tap digitally controlled potentiometer (DCP) with SPI interface, 10kΩ total resistance, 1.7V–5.5V analog supply (VCC), and independent 1.2V–5.5V logic supply (VLOGIC). It operates across –40°C to +125°C and features 70Ω typical wiper resistance at 3.3V, used for precision gain adjustment in battery-powered instrumentation.
For engineers reviewing the ISL23428WFVZ-T7A datasheet, ISL23428WFVZ-T7A pinout, ISL23428WFVZ-T7A application, or ISL23428WFVZ-T7A equivalent, key selection criteria include its dual-channel 10kΩ DCP architecture, SPI-compatible low-voltage operation down to 1.2V logic, mid-scale power-on reset, and shutdown mode enabling end-to-end open-circuit isolation.
Technical Context
The ISL23428WFVZ-T7A integrates two independent DCP cores on a monolithic CMOS IC, each controlled via an 8-bit volatile Wiper Register (WR0/WR1) accessible through a Mode-0 SPI interface. Wiper positioning uses make-before-break switching, ensuring monotonic resistance transitions between RH, RW, and RL terminals.
It supports voltage divider and rheostat configurations, with guaranteed ±0.15 LSB INL/DNL (10kΩ option), 125 ppm/°C end-to-end tempco, and ratiometric tempco as low as 8 ppm/°C. Shutdown mode disconnects DCP resistors and internally connects RW to RL via a 2kΩ path, reducing system leakage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 10kΩ - defines full-scale analog range for gain/offset trimming in sensor or amplifier circuits. |
| Wiper Resistance | 70Ω typical @ 3.3V - limits insertion error and signal attenuation in precision voltage-divider applications. |
| VCC Supply Range | 1.7V to 5.5V - enables direct integration into mixed-supply systems including Li-ion battery rails (2.7–4.2V) and 3.3V/5V domains. |
| VLOGIC Range | 1.2V to 5.5V - allows native interfacing with ultra-low-voltage MCUs (e.g., ARM Cortex-M0+) without level shifters. |
| Temperature Range | –40°C to +125°C - qualified for under-hood automotive, industrial motor control, and harsh-environment sensor conditioning. |
| Shutdown Current | 1.2µA @ VCC = VLOGIC = 1.7V - minimizes quiescent drain in always-on battery-backed systems during sleep states. |
| Settling Time | 300ns large-signal wiper settling - supports dynamic recalibration in closed-loop bias control loops (e.g., RF PA compensation). |
Pinout & Package
ISL23428WFVZ-T7A is packaged in a 14-lead TSSOP (RoHS-compliant, M14.173 footprint), with exposed pad not electrically connected. Pin functions are validated per FN7904 Rev 2.00 datasheet.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1, 7 | GND | Analog and digital ground reference; requires low-impedance connection to minimize noise coupling between DCP channels. |
| 2 | VLOGIC | Dedicated logic supply input; powers SPI interface and internal level translator-decoupled from VCC for mixed-voltage system compatibility. |
| 3 | SDO | SPI data output; push-pull by default (ACR[1]=0); configurable to open-drain for wired-OR bus topologies. |
| 4 | SCK | SPI clock input; rising-edge sampled; supports up to 5MHz (≥1.7V VLOGIC) or 1MHz (1.2–1.6V). |
| 5 | SDI | SPI data input; accepts instruction + data bytes (MSB-first) for WR0/WR1/ACR register access. |
| 6 | CS | Active-low chip select; must transition HIGH→LOW before each SPI transaction; controls standby/shutdown entry timing. |
| 8 | RL1 | DCP1 low terminal; forms one end of 10kΩ resistor string; referenced to GND in standard voltage-divider use. |
| 9 | RW1 | DCP1 wiper terminal; outputs interpolated voltage/resistance; subject to 70Ω series resistance and ±3mA max current. |
| 10 | RH1 | DCP1 high terminal; forms other end of 10kΩ string; voltage must remain ≤ VCC to avoid latch-up. |
| 11 | RH0 | DCP0 high terminal; electrically isolated from RH1; enables independent dual-channel configuration. |
| 12 | RW0 | DCP0 wiper terminal; shares same SPI interface but separate WR0 register; supports channel-matching within ±0.5 LSB. |
| 13 | RL0 | DCP0 low terminal; paired with RW0/RH0; allows simultaneous trimming of two signal paths (e.g., differential gain stages). |
| 14 | VCC | Analog supply input; powers DCP resistor array and wiper switches; independent of VLOGIC for rail-flexible design. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 128-tap DCPs | Enables concurrent calibration of two analog signal chains (e.g., I/Q paths, dual-sensor front-ends) with matched tempcos and INL. |
| VLOGIC = 1.2V support | Eliminates external level shifters when interfacing with sub-1.8V microcontrollers, reducing BOM count and layout complexity. |
| Mid-scale power-on reset (64) | Guarantees known initial state (50% resistance) at startup-critical for fail-safe biasing in power supply margining circuits. |
| Shutdown mode with RW–RL short | Forces open-circuit DCP terminals while maintaining wiper position; prevents unintended loading during system sleep or fault conditions. |
| ±0.15 LSB INL/DNL (10kΩ) | Ensures high linearity for closed-loop feedback applications where tap-to-tap step accuracy directly impacts control stability. |
| 125 ppm/°C end-to-end tempco | Minimizes drift-induced gain error over temperature in precision sensor signal conditioning (e.g., RTD or strain gauge bridges). |
Applications
| Power Supply Margining | RF Power Amplifier Bias Compensation |
|---|---|
|
Use Scenario: Adjusting reference voltage thresholds in DC-DC converter feedback networks to validate tolerance margins during production test. IC Role / Device Role / Timing Role: Dual DCP provides independent fine-tuning of upper/lower margin limits using WR0/WR1 registers via SPI host controller. Use Value: Enables automated, software-controlled margin testing without manual trimmer replacement-reducing test time and human error. |
Use Scenario: Dynamically compensating for temperature-induced gain drift in GaN RF power amplifiers across –40°C to +125°C ambient. IC Role / Device Role / Timing Role: ISL23428WFVZ-T7A acts as programmable bias resistor network, with one DCP setting gate voltage and the other adjusting source degeneration. Use Value: Achieves <±0.5 LSB matching between channels, maintaining amplitude flatness and minimizing EVM degradation over temperature. |
| Trimming Sensor Circuits | Gain Adjustment in Battery-Powered Instruments |
|
Use Scenario: Calibrating offset and span in industrial pressure transducer signal chains using factory-programmed lookup tables. IC Role / Device Role / Timing Role: Configured in rheostat mode (RW–RL), ISL23428WFVZ-T7A adjusts bridge excitation current or op-amp feedback ratio. Use Value: 10kΩ resistance and 125 ppm/°C tempco ensure stable calibration over extended field life-meeting ISO 5167 repeatability requirements. |
Use Scenario: Optimizing audio codec gain stages in portable medical ultrasound devices to maximize SNR while conserving battery energy. IC Role / Device Role / Timing Role: Dual DCP trims both pre-amplifier and filter stage gains; low 4µA standby current extends runtime between charges. Use Value: 1.2V VLOGIC compatibility allows direct connection to 1.2V SoC GPIOs-removing level-shifter losses and simplifying PCB routing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5242BRUZ10 | Single 256-tap, I²C interface, 10kΩ, 2.7–5.5V supply; no VLOGIC separation; higher 150 ppm/°C tempco. | Lacks dual-channel capability and independent logic supply-requires level shifting for sub-1.8V hosts. | Choose when I²C is preferred over SPI and single-channel operation suffices; verify tempco impact on long-term calibration stability. |
| MCP42010-I/P | Dual 256-tap, SPI interface, 10kΩ, 2.7–5.5V supply only; no VLOGIC pin; 100 ppm/°C tempco; 14-pin PDIP package. | No low-voltage logic support; larger through-hole package incompatible with space-constrained portable designs. | Select for legacy through-hole assembly or where 256-tap resolution justifies trade-offs in voltage flexibility and package size. |
Compared with AD5242BRUZ10 and MCP42010-I/P, the ISL23428WFVZ-T7A uniquely delivers dual 128-tap DCPs with true 1.2V logic compatibility and mid-scale power-on reset-enabling robust, low-power, and space-efficient trimming in modern embedded systems.
Availability
ISL23428WFVZ-T7A is available at Aetrix Electronics and suitable for power supply margining, RF amplifier biasing, sensor trimming, and battery-powered instrumentation requiring stable component supply across extended temperature ranges.
Supply support for ISL23428WFVZ-T7A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and maintains full technical and supply chain support for legacy Intersil precision analog products.
The ISL23428 belongs to Renesas' XDCP™ (eXternally Digitally Controlled Potentiometer) family, designed specifically for replacing mechanical trimmers in high-reliability, programmable analog signal conditioning applications.
FAQ
What is the total resistance value of the ISL23428WFVZ-T7A?
The ISL23428WFVZ-T7A has a nominal total resistance of 10kΩ between RH and RL terminals for both integrated potentiometers. This value is confirmed in the Ordering Information table (W option) and Analog Specifications section of FN7904 Rev 2.00, with ±20% tolerance over temperature and voltage.
Does the ISL23428WFVZ-T7A retain wiper settings after power cycling?
No-the ISL23428WFVZ-T7A contains volatile wiper registers (WR0 and WR1). Upon power-up, both wipers reset to mid-scale (64 decimal, 40h), regardless of prior state. Non-volatile alternatives require external EEPROM or microcontroller-based storage of register values.
Can the ISL23428WFVZ-T7A operate with different voltages on VCC and VLOGIC simultaneously?
Yes-the ISL23428WFVZ-T7A explicitly supports independent supplies: VCC from 1.7V to 5.5V for analog circuitry and VLOGIC from 1.2V to 5.5V for SPI interface logic. This decoupling allows direct connection to low-voltage MCUs while powering DCPs from higher analog rails.
What is the maximum allowable current through the wiper terminal of the ISL23428WFVZ-T7A?
The absolute maximum wiper current for the ISL23428WFVZ-T7A is ±6mA for 10 seconds (per Absolute Maximum Ratings), but the Recommended Operating Conditions specify ±3mA continuous. Exceeding ±3mA risks increased wiper resistance drift and long-term reliability degradation.
How does the shutdown mode function in the ISL23428WFVZ-T7A?
In shutdown mode (enabled via SHDN bit in ACR), the ISL23428WFVZ-T7A disconnects both DCP resistor strings from RH–RL paths and internally connects each RW to its corresponding RL through a 2kΩ resistor. This preserves wiper register values while isolating the DCP from the circuit.
ISL23428WFVZ-T7A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 128
- Resistance (Ohms):
- 10k
- Interface:
- SPI
- Memory Type:
- Volatile
- Voltage - Supply:
- 1.2V ~ 5.5V, 1.7V ~ 5.5V
- Features:
- -
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- 125ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 14-TSSOP
- Operating Temperature:
- -40°C ~ 125°C
- Resistance - Wiper (Ohms) (Typ):
- 70
ISL23428WFVZ-T7A FAQ
1.How can I place an order for ISL23428WFVZ-T7A through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL23428WFVZ-T7A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL23428WFVZ-T7A reliable?
The price and inventory of ISL23428WFVZ-T7A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL23428WFVZ-T7A is usually 5 days.
3.What payment methods are accepted for ISL23428WFVZ-T7A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL23428WFVZ-T7A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL23428WFVZ-T7A?
ISL23428WFVZ-T7A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL23428WFVZ-T7A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL23428WFVZ-T7A?
For technical support, including ISL23428WFVZ-T7A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL23428WFVZ-T7A requirements.
6.How does Aetrix verify that ISL23428WFVZ-T7A is sourced from the original manufacturer or authorized distributors?
All ISL23428WFVZ-T7A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL23428WFVZ-T7A meets industry standards.
7.What is the process for return or replacement of ISL23428WFVZ-T7A?
All ISL23428WFVZ-T7A units undergo pre-shipment inspection (PSI). If there is an issue with ISL23428WFVZ-T7A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL23428WFVZ-T7A part is unused and in its original packaging.
Return procedure for ISL23428WFVZ-T7A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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