Renesas ISL23428WFVZ-TK
- Part No.:
- ISL23428WFVZ-TK
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ISL23428WFVZ-TK.pdf
- Description:
- IC DGT POT 10KOHM 128TAP 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL23428WFVZ-TK from Renesas Electronics (formerly Intersil) is a dual, volatile, 128-tap digitally controlled potentiometer with SPI interface, 10kΩ total resistance, 1.7V–5.5V analog supply (VCC), and independent 1.2V–5.5V logic supply (VLOGIC). It operates across –40°C to +125°C and delivers 70Ω typical wiper resistance at 3.3V, enabling precision trimming in battery-powered sensor circuits and RF bias networks.
For engineers reviewing the ISL23428WFVZ-TK datasheet, ISL23428WFVZ-TK pinout, ISL23428WFVZ-TK application, or ISL23428WFVZ-TK equivalent, key selection criteria include its dual-channel 10kΩ DCP architecture, VLOGIC-independent low-voltage SPI operation down to 1.2V, mid-scale power-on default (64 tap), shutdown mode with end-to-end open circuit, and TSSOP-14 package compatibility for space-constrained industrial control and portable instrumentation designs.
Technical Context
The ISL23428WFVZ-TK integrates two independent DCP cores on a monolithic CMOS die, each with an 8-bit volatile Wiper Register (WR0/WR1) directly accessible via SPI Mode 0 (rising-edge clock-in, falling-edge clock-out). Its "make-before-break" switch architecture ensures glitch-free wiper transitions during tap changes.
It supports voltage divider and rheostat configurations, with guaranteed monotonicity, ±0.15 LSB INL/DNL (10kΩ option), and ratiometric temperature coefficient as low as 8 ppm/°C. The VLOGIC pin decouples digital interface voltage from analog supply, eliminating level shifters when interfacing with 1.2V–1.8V microcontrollers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 10kΩ - Enables precise gain/offset adjustment in low-voltage signal chains without excessive current draw. |
| Taps per Potentiometer | 128 - Provides 7.8 mV/LSB resolution in 3.3V divider mode, supporting fine-grained calibration. |
| VCC Supply Range | 1.7V to 5.5V - Supports direct connection to Li-ion battery rails (2.7–4.2V) or 3.3V/5V system supplies. |
| VLOGIC Supply Range | 1.2V to 5.5V - Allows native SPI communication with ultra-low-voltage MCUs (e.g., ARM Cortex-M0+) without external level translation. |
| Wiper Resistance | 70Ω typical @ 3.3V - Minimizes loading error in high-impedance feedback paths (e.g., op-amp gain-setting networks). |
| Shutdown Current | 1.2µA @ VCC = VLOGIC = 1.7V - Extends battery life in always-on sensor nodes by disabling DCP resistive path while retaining WR state. |
| Operating Temperature | –40°C to +125°C - Qualified for under-hood automotive, industrial motor drives, and outdoor telecom equipment. |
Pinout & Package
ISL23428WFVZ-TK is housed in a RoHS-compliant, 14-lead TSSOP package (M14.173), optimized for automated assembly and thermal performance (θJA = 112°C/W).
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1, 7 | GND | Analog and digital ground reference; requires low-impedance PCB connection to minimize noise coupling into DCP terminals. |
| 2 | VLOGIC | Digital supply input for SPI interface; sets logic threshold levels independently of VCC, enabling mixed-voltage system integration. |
| 3 | SDO | Configurable serial data output (Push-Pull default); tri-states when CS is HIGH, allowing daisy-chaining of multiple DCPs on one bus. |
| 4 | SCK | SPI clock input; accepts up to 5 MHz (≥1.7V VLOGIC) for fast wiper updates in closed-loop systems. |
| 5 | SDI | SPI data input; latches instruction/data on rising SCK edge; supports write-to-WR0/WR1 or ACR configuration. |
| 6 | CS | Active-low chip select; must transition LOW before SCK activity; initiates standby mode when HIGH. |
| 8 | RL1 | DCP1 low terminal; connects to circuit ground or reference node in voltage divider mode. |
| 9 | RW1 | DCP1 wiper output; delivers adjustable voltage/resistance; routed to op-amp input or bias node with minimal parasitic capacitance (32pF). |
| 10 | RH1 | DCP1 high terminal; ties to VCC or positive reference; forms upper leg of 10kΩ resistor ladder. |
| 11 | RH0 | DCP0 high terminal; electrically isolated from RH1; enables independent scaling of two signal paths. |
| 12 | RW0 | DCP0 wiper output; shares same timing and resolution specs as RW1; supports dual-sensor offset correction. |
| 13 | RL0 | DCP0 low terminal; may be tied to separate ground plane for noise isolation in mixed-signal layouts. |
| 14 | VCC | Analog supply input; powers resistor array and wiper switches; must be filtered locally to suppress supply-induced wiper noise. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 128-tap DCPs | Enables simultaneous calibration of two independent analog channels (e.g., differential sensor pairs or dual-path amplifiers) within one footprint. |
| VLOGIC/VCC voltage separation | Eliminates external level shifters when interfacing with sub-1.8V logic, reducing BOM count and layout complexity in ultra-low-power designs. |
| Mid-scale power-on reset (64) | Guarantees known initial wiper position at startup, preventing transient overvoltage or undefined bias conditions in sensitive front-end circuits. |
| Shutdown mode with internal RL short | Forces open-circuit between RH–RW while connecting RW to RL via 2kΩ, safely isolating DCP from signal path without external FETs or relays. |
| ±0.15 LSB INL/DNL (10kΩ) | Ensures accurate voltage division across full temperature range, critical for factory-trimmed medical instrumentation and test equipment. |
| 1.2V minimum VLOGIC | Supports direct connection to energy-harvesting PMUs or 1.2V FPGA I/O banks, extending usability in batteryless IoT edge nodes. |
Applications
| Power Supply Margining | RF Power Amplifier Bias Compensation |
|---|---|
Use Scenario: Adjusting feedback resistors in DC-DC converter error amplifiers to validate stability margins across voltage/temp corners. IC Role / Device Role / Timing Role: Dual DCP provides independent high-side and low-side resistor trimming for precise VOUT setpoint tuning. Use Value: Replaces manual trim pots with programmable, repeatable calibration; eliminates post-manufacturing rework and supports remote firmware updates. |
Use Scenario: Dynamically compensating for temperature-induced gain drift in GaN RF PAs used in 5G base stations. IC Role / Device Role / Timing Role: ISL23428WFVZ-TK adjusts gate bias voltage via voltage divider to maintain constant output power across –40°C to +125°C. Use Value: 8 ppm/°C ratiometric TCv ensures stable bias point; shutdown mode disables bias path during PA sleep cycles, cutting leakage current. |
| Trimming Sensor Circuits | Gain Adjustment in Battery-Powered Instruments |
Use Scenario: Nulling offset voltage in MEMS accelerometer signal conditioning stages during production calibration. IC Role / Device Role / Timing Role: One DCP sets zero-bias voltage at op-amp input; second DCP adjusts gain-setting resistor ratio. Use Value: 128-tap resolution achieves <10 µV offset correction accuracy; 70Ω wiper resistance prevents loading of high-Z sensor outputs. |
Use Scenario: Scaling full-scale range of handheld multimeters powered by two AA cells (1.8–3.2V). IC Role / Device Role / Timing Role: ISL23428WFVZ-TK configures programmable gain amplifier (PGA) feedback network to match input signal amplitude. Use Value: 1.7V VCC minimum allows operation down to battery EOL; 4µA standby current extends runtime beyond 1000 hours. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5242BRUZ10 | Single 10kΩ DCP, I²C interface, 24-lead TSSOP, 20ppm/°C tempco, no VLOGIC independence. | Lacks dual-channel capability and 1.2V logic compatibility; requires level shifter for sub-1.8V hosts. | Select when I²C bus is preferred and single-pot functionality suffices; verify layout space for larger package. |
| MCP42010-I/P | Dual 10kΩ DCP, SPI interface, 14-lead PDIP (not surface-mount), 50ppm/°C tempco, no shutdown mode. | Through-hole only; higher tempco degrades precision over temperature; no power-gating capability. | Choose only for prototyping or legacy through-hole designs; unsuitable for automated SMT production or extended-temp applications. |
Compared with AD5242BRUZ10 and MCP42010-I/P, the ISL23428WFVZ-TK uniquely combines dual 10kΩ DCPs, 1.2V–5.5V VLOGIC support, shutdown mode with internal RL short, and –40°C to +125°C qualification-making it optimal for compact, battery-sensitive, and thermally demanding embedded systems.
Availability
ISL23428WFVZ-TK is available at Aetrix Electronics and suitable for power supply margining, RF amplifier bias compensation, sensor trimming, and portable instrument gain adjustment requiring stable component supply across industrial and automotive temperature ranges.
Supply support for ISL23428WFVZ-TK includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics acquired Intersil in 2017 and maintains full product support for the ISL23428 family. Renesas is a global semiconductor leader focused on microcontrollers, analog, power, and connectivity solutions.
The ISL23428 series was designed specifically for precision analog trimming in space-constrained, low-power, and wide-temperature applications-targeting industrial automation, automotive subsystems, and portable test equipment where mechanical potentiometers fail.
FAQ
What is the total resistance value specified for the ISL23428WFVZ-TK?
The ISL23428WFVZ-TK is configured with a 10kΩ total resistance (RH to RL) per potentiometer, as indicated by the 'W' in the part number per the ordering information table. This value is fixed at manufacture and cannot be changed via software or configuration bits.
Does the ISL23428WFVZ-TK retain wiper settings after power cycling?
No-the ISL23428WFVZ-TK contains volatile Wiper Registers (WR0 and WR1). Upon power-up, both wipers reset to the mid-scale position (64 decimal, or 0x40), regardless of prior state. Non-volatile storage requires external EEPROM or MCU-based register restoration.
Can the ISL23428WFVZ-TK operate with different voltages on VCC and VLOGIC simultaneously?
Yes-the ISL23428WFVZ-TK explicitly supports independent supplies: VCC from 1.7V to 5.5V for the analog DCP section, and VLOGIC from 1.2V to 5.5V for the digital SPI interface. This allows direct interfacing with 1.2V logic while powering the resistor array from 3.3V or 5V.
What happens to the DCP terminals during shutdown mode activation?
When the SHDN bit in the Access Control Register is set to 0, the ISL23428WFVZ-TK forces an open circuit between RH and RW for both DCPs, while internally connecting each RW to its corresponding RL through a 2kΩ resistor. This isolates the potentiometer from the signal path while preserving WR register contents.
Is the ISL23428WFVZ-TK pin-compatible with other variants in the ISL23428 family?
Yes-all ISL23428 variants in the 14-lead TSSOP package (e.g., ISL23428TFVZ-TK, ISL23428UFVZ-TK, ISL23428WFVZ-TK) share identical pinouts and footprints. Only the total resistance (10kΩ/50kΩ/100kΩ) and marking differ; no PCB redesign is needed when substituting within the same package option.
ISL23428WFVZ-TK Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 128
- Resistance (Ohms):
- 10k
- Interface:
- SPI
- Memory Type:
- Volatile
- Voltage - Supply:
- 1.2V ~ 5.5V, 1.7V ~ 5.5V
- Features:
- -
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- 125ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 14-TSSOP
- Operating Temperature:
- -40°C ~ 125°C
- Resistance - Wiper (Ohms) (Typ):
- 70
ISL23428WFVZ-TK FAQ
1.How can I place an order for ISL23428WFVZ-TK through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL23428WFVZ-TK on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL23428WFVZ-TK reliable?
The price and inventory of ISL23428WFVZ-TK are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL23428WFVZ-TK is usually 5 days.
3.What payment methods are accepted for ISL23428WFVZ-TK?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL23428WFVZ-TK transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL23428WFVZ-TK?
ISL23428WFVZ-TK orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL23428WFVZ-TK order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL23428WFVZ-TK?
For technical support, including ISL23428WFVZ-TK datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL23428WFVZ-TK requirements.
6.How does Aetrix verify that ISL23428WFVZ-TK is sourced from the original manufacturer or authorized distributors?
All ISL23428WFVZ-TK products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL23428WFVZ-TK meets industry standards.
7.What is the process for return or replacement of ISL23428WFVZ-TK?
All ISL23428WFVZ-TK units undergo pre-shipment inspection (PSI). If there is an issue with ISL23428WFVZ-TK, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL23428WFVZ-TK part is unused and in its original packaging.
Return procedure for ISL23428WFVZ-TK:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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