Renesas ISL26102AVZ-T7A

Overview

ISL26102AVZ-T7A from Renesas (formerly Intersil) is a 24-bit delta-sigma analog-to-digital converter with integrated programmable gain amplifier (PGA), two fully differential multiplexed input channels, and automotive-grade operation (-40°C to +105°C). It delivers 21.5 noise-free bits at 10 Sps, supports PGA gains from 1× to 128×, and features low-side power switch (LSPS) for load cell bias control. It is used in high-accuracy weigh scale front-ends where direct sensor interface and ±19.5 mV_FS full-scale resolution at PGA=128 are required.

For engineers reviewing the ISL26102AVZ-T7A datasheet, ISL26102AVZ-T7A pinout, ISL26102AVZ-T7A application, or ISL26102AVZ-T7A equivalent, key selection criteria include noise performance (7 nV/√Hz @ PGA=128), input-referred RMS noise down to 6.5 nV at 4 kSps, 0.0002% FS linearity, 24 Ld TSSOP package compatibility, and support for external crystal (4.9152 MHz) or internal oscillator clocking.

Technical Context

The ISL26102AVZ-T7A integrates a chopper-stabilized PGA with seven discrete gain settings (1×–128×) and a third-order delta-sigma modulator followed by a programmable SINC4 digital filter. Its input stage supports ±0.5 V_REF/Gain differential span, with common-mode range extending to rails only at 1× gain.

It provides on-chip temperature sensing and AVDD monitoring via internal channel selection, and includes register-controlled LSPS output for load-cell power management. Serial interface uses SPI-compatible protocol with CS, SCLK, SDI, and SDO/RDY signals, supporting 24-bit two's complement data output at selectable word rates from 2.5 to 4000 Sps.

Key Specifications

Pinout & Package

ISL26102AVZ-T7A is housed in a 24-lead Thin Shrink Small Outline Package (TSSOP), Pb-free, RoHS-compliant, with thermal resistance θ_JA = 65°C/W and θ_JC = 18°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar precision delta-sigma ADC applications.

Compared with ADS124S08IPW and AD7172-2BRUZ, the ISL26102AVZ-T7A uniquely combines metrology-grade noise performance, integrated LSPS, on-chip diagnostics, and compact 24-lead TSSOP-making it optimal for space-constrained, self-contained industrial weigh modules.

Availability

ISL26102AVZ-T7A is available at Aetrix Electronics and suitable for weigh scales, industrial process control, and load safety systems requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ISL26102AVZ-T7A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation acquired Intersil in 2017 and maintains full product support, documentation, and manufacturing continuity for legacy Intersil precision analog ICs.

The ISL26102AVZ-T7A belongs to Renesas' high-accuracy delta-sigma ADC family designed specifically for industrial metrology, automotive weight sensing, and sensor signal conditioning where low noise, gain flexibility, and system integration reduce total solution cost.

FAQ

What is the maximum output word rate supported by the ISL26102AVZ-T7A?

The ISL26102AVZ-T7A supports an output word rate of up to 4000 samples per second (Sps) when driven by a 4.9152 MHz clock source. At this rate, noise-free resolution drops to 17.6 bits, and RMS input-referred noise rises to 194.9 nV. The actual achievable rate scales linearly with clock frequency - for example, using a 2.4576 MHz clock halves all listed word rates. The OWR register (address 05h) configures the selected rate via hex code 13h for 4000 Sps.

Does the ISL26102AVZ-T7A require external passive components for stable operation?

Yes, the ISL26102AVZ-T7A requires two external 100 nF C0G ceramic capacitors connected between CAP pins (9 and 10) to implement the PGA's RC filter and suppress chopping artifacts. It also needs local 100 nF + 10 µF decoupling on AVDD (Pin 18) and DVDD (Pins 1, 6), plus proper grounding separation between AGND and DGND. No external crystal load capacitors are needed - internal capacitance is optimized for 4.9152 MHz operation.

How does the low-side power switch (LSPS) function in the ISL26102AVZ-T7A?

The LSPS pin (Pin 19) is an open-drain output controlled by bit b0 of the SDO/LSPS register (address 82h). When set to logic 1, it sinks up to 30 mA with typical R_ON of 10 Ω, enabling direct drive of load-cell excitation circuits. It automatically disables during power-down or standby modes. This eliminates the need for external MOSFET drivers in weigh-scale designs, simplifying layout and improving reliability.

Can the ISL26102AVZ-T7A measure its own supply voltage and temperature?

Yes, the ISL26102AVZ-T7A includes dedicated internal channels for both AVDD monitoring and on-chip temperature sensing. These are selected via the Input Mux Selection register (address 07h): codes 100b and 101b respectively. When either is selected, the PGA gain is automatically forced to 1×, and measurements appear as 24-bit signed integers scaled per datasheet specifications - no external components required.

What are the absolute maximum ratings for analog input voltage on the ISL26102AVZ-T7A?

The absolute maximum analog input voltage on the ISL26102AVZ-T7A is limited to AGND – 0.3 V to AVDD + 0.3 V. Within operational conditions, the differential input voltage range is ±0.5 V_REF/Gain (e.g., ±19.5 mV at PGA=128 with 5 V reference), and the common-mode input range varies with gain: AGND + 0.1 V to AVDD – 0.1 V at gain=1, or AGND + 1.5 V to AVDD – 1.5 V at gains ≥2. Exceeding these violates safe operating area and may cause latch-up.