Renesas ISL6128IR-T

Overview

ISL6128IR-T from Intersil is a 4-channel power-supply sequencer with dual independent 2-channel groupings (A/B and C/D), each with dedicated ENABLE and RESET I/O, designed for redundant-load voltage sequencing in multi-rail systems. It operates from 1.5V to 5.5V bias, delivers VDD+5.3V gate drive, supports adjustable slew via external capacitors on DLY_ON/DLY_OFF pins, and provides undervoltage lockout monitoring on all four rails. It is used in FPGA/ASIC power domains requiring fault-isolated sequencing.

For engineers reviewing the ISL6128IR-T datasheet, ISL6128IR-T pinout, ISL6128IR-T application, or ISL6128IR-T equivalent, key selection criteria include dual-group fault independence, 24-lead QFN package compatibility, programmable turn-on/off delays per rail, and support for cascaded SYSRST signaling across multiple sequencers.

Technical Context

The ISL6128IR-T implements two independent 2-channel sequencing groups: ENABLE_1 controls GATE_A/GATE_B and ENABLE_2 controls GATE_C/GATE_D. All four UVLO inputs must be satisfied before sequencing begins, but a fault in one group (e.g., UVLO_A violation) only pulls down GATE_A/GATE_B and RESET_2 - leaving the C/D group fully operational.

Sequencing timing is set by external capacitors on DLY_ON_X and DLY_OFF_X pins, each charged by a 1µA current source to a 1.266V threshold; turn-on delay per rail is nominally 1.3 seconds per µF. The internal charge pump generates VDD+5.3V gate drive, enabling robust N-channel MOSFET control even at low VDD (1.5V).

Key Specifications

Pinout & Package

ISL6128IR-T uses a 24-lead 4×4 mm Pb-free QFN package with exposed EPAD for thermal dissipation. Pin functions are validated per FN9005 Rev 1.00 datasheet Figure 3 (ISL6128 top view) and Pin Descriptions (Page 4).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar power-supply sequencing applications.

Compared with ISL6126IRZA and ISL6130IRZA, the ISL6128IR-T uniquely provides hardware-enforced fault isolation between two 2-rail groups via dedicated ENABLE/RESET signals - essential for redundant, high-availability systems where partial failure must not compromise backup functionality.

Availability

ISL6128IR-T is available at Aetrix Electronics and suitable for FPGA/ASIC power domain sequencing, telecom line card sequencing, and industrial PLC backplane power management requiring stable component supply and long-term production continuity.

Supply support for ISL6128IR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Intersil (now part of Renesas Electronics) is a semiconductor company specializing in precision analog, power management, and interface ICs for industrial, communications, and computing markets.

The ISL6128IR-T belongs to the ISL612X family of programmable 4-channel power sequencers, designed specifically for high-reliability, multi-rail systems requiring configurable timing, fault containment, and cascaded control in space-constrained PCB layouts.

FAQ

What is the function of ENABLE_2 on the ISL6128IR-T?

ENABLE_2 is the dedicated active-low enable input for the C/D channel group. When pulled low (with all four UVLO inputs satisfied), it initiates sequencing for GATE_C and GATE_D. Its independence from ENABLE_1 allows isolated control - for example, enabling the C/D group while holding A/B in reset. This is fundamental to the ISL6128IR-T's dual-group redundancy architecture.

Does the ISL6128IR-T support daisy-chaining with other sequencers?

Yes, the ISL6128IR-T supports daisy-chaining via the SYSRST pin. When SYSRST is driven low (e.g., due to a UVLO fault), it unconditionally latches off all GATE outputs and pulls low any other SYSRST pins connected in parallel - enabling synchronized shutdown across multiple ISL612X devices. This behavior is confirmed in the FN9005 datasheet Section "SYSRST" on Page 4.

What is the maximum gate drive voltage provided by the ISL6128IR-T?

The ISL6128IR-T provides a charge-pumped gate drive voltage of VDD + 5.3V, with typical values of VDD + 4.9V at VDD < 2V and VDD + 5.0V to VDD + 5.3V at VDD > 2V. This is specified in the Electrical Specifications table (Page 7) under "GATE High Voltage", ensuring full enhancement of standard N-channel MOSFETs across the full 1.5V–5.5V VDD range.

How does fault isolation work between groups on the ISL6128IR-T?

Fault isolation is hardware-enforced: a UVLO violation on UVLO_A or UVLO_B pulls low only GATE_A, GATE_B, and RESET (global), while leaving GATE_C, GATE_D, and RESET_2 unaffected. Similarly, a C/D group fault affects only its own gates and RESET_2. This behavior is explicitly defined in the Variant Feature Matrix (Page 5) and confirmed in the "Descriptions and Operation" section (Page 8) of the FN9005 datasheet.

Can the ISL6128IR-T sequence rails with different voltage thresholds?

Yes. Each UVLO_A–D input accepts a resistor divider from its target rail, referenced to the internal 633 mV threshold. By selecting appropriate resistor ratios, rails from 0.7V to 5V can be monitored independently - e.g., 1.2V rail with ~1.9× divider, 3.3V rail with ~5.2× divider. This flexibility is documented in the "Features" list (Page 1) and "UVLO" electrical specifications (Page 6).