Renesas ISL6128IRZA

Overview

ISL6128IRZA from Intersil is a 4-channel power-supply sequencer with dual independent 2-channel grouping, enabling redundant voltage sequencing for fault-isolated operation. It features two ENABLE inputs (ENABLE_1 for channels A/B, ENABLE_2 for C/D), four UVLO monitoring inputs, programmable turn-on/off delays via external capacitors, and charge-pump gate drive delivering VDD + 5.3V to external NFETs. It operates from 1.5V to 5.5V supply and supports systems requiring independent group-level sequencing and fault containment - such as dual-redundant FPGA core/IO rail supplies.

For engineers reviewing the ISL6128IRZA datasheet, ISL6128IRZA pinout, ISL6128IRZA application, or ISL6128IRZA equivalent, this page provides verified technical context, confirmed pin functions, real-world sequencing behavior, exact package mapping (24 Ld 4×4 QFN), and validated alternative options for redundant power sequencing designs.

Technical Context

The ISL6128IRZA implements dual-group sequencing: all four UVLO inputs must be satisfied *and* both ENABLE_1 and ENABLE_2 asserted low before sequencing begins; then Group A/B turns on first (A→B), followed by Group C/D (C→D). Each group has dedicated RESET_2 output and independent fault response - a UVLO fault in Group C/D pulls only GATE_C/GATE_D and RESET_2 low, leaving Group A/B operational.

Sequencing timing is controlled by external capacitors on DLY_ON_A/B/C/D and DLY_OFF_A/B/C/D pins, each charged/discharged by a 1µA current source to a 1.266V threshold; gate drive uses an internal micropower 7× charge pump to deliver VDD + 5.3V (min) to external NFET gates, supporting soft-start ramp control and glitch-immune operation with 30µs transient filtering on all UVLO/ENABLE inputs.

Key Specifications

Pinout & Package

ISL6128IRZA is housed in a 24-lead, 4 mm × 4 mm, 0.5 mm pitch QFN package (Pb-free, RoHS-compliant) with exposed thermal pad (EPAD) for enhanced thermal performance. Pinout is fully defined in datasheet Figure 3 (ISL6128 TOP VIEW) and Pin Descriptions table (Page 4).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 4-channel power sequencing applications.

Compared with ISL6126IRZA and TPS652860RHAR, the ISL6128IRZA uniquely delivers hardware-enforced dual-group fault isolation, user-programmable delays per channel, and discrete gate drive flexibility - making it the only option for true N+1 redundant sequencing where group-level continuity is mandatory.

Availability

ISL6128IRZA is available at Aetrix Electronics and suitable for telecom line cards, FPGA dual-rail power systems, industrial PLC backplanes, and redundant server motherboards requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for ISL6128IRZA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Intersil (now part of Renesas Electronics) is a semiconductor company specializing in precision analog, power management, and interface ICs for industrial, telecom, and computing applications.

The ISL6128IRZA belongs to the ISL612X family of programmable 4-channel power sequencers, designed specifically for high-reliability systems requiring fault-isolated, capacitor-tuned voltage sequencing across redundant power domains.

FAQ

What is the function of ENABLE_2 on the ISL6128IRZA?

ENABLE_2 is the dedicated active-low enable input for Group C/D (channels C and D) on the ISL6128IRZA. Both ENABLE_1 (for Group A/B) and ENABLE_2 must be asserted low simultaneously to initiate sequencing. After a UVLO fault in Group C/D, ENABLE_2 must be cycled (toggled) to restart that group - ensuring fault containment without affecting Group A/B operation.

Does the ISL6128IRZA support independent turn-off sequencing per group?

Yes, the ISL6128IRZA supports independent turn-off sequencing per group. When ENABLE_1 goes high, Group A/B shuts down in reverse order (B then A); when ENABLE_2 goes high, Group C/D shuts down in reverse order (D then C). DLY_OFF capacitors set individual delays within each group, and a fault in one group does not trigger shutdown of the other.

Can the ISL6128IRZA drive standard logic-level NFETs directly?

Yes, the ISL6128IRZA can drive standard logic-level NFETs directly. Its charge-pump gate drive delivers VDD + 5.3V (minimum), which exceeds the 4.5V VGS(th) threshold of most logic-level NFETs - even when biased from low VDD (e.g., 1.5V → 6.8V gate drive). No external level-shifting circuitry is required.

How does RESET_2 differ from RESET on the ISL6128IRZA?

RESET is the global sequence completion signal, asserting low until all four GATEs reach VDD + 5.3V and 160 ms stabilization elapses. RESET_2 is exclusive to Group C/D: it asserts low only when a UVLO fault occurs in that group or when ENABLE_2 is deasserted - allowing system firmware to distinguish between primary (A/B) and backup (C/D) rail faults without ambiguity.

What is the minimum external capacitor value recommended for DLY_ON timing on ISL6128IRZA?

The datasheet specifies a nominal 100 pF minimum for DLY_ON timing on ISL6128IRZA. At this value, the delay from DLY_ON pin start-of-charge to GATE ramp initiation is ~130 ns (calculated as 100 pF × 1.3 MΩ). Smaller values risk timing uncertainty due to parasitic capacitance; 100 pF provides reliable sub-microsecond resolution while maintaining noise immunity.