Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Special Purpose Regulators

Renesas ISL6225CA

Name: ISL6225CA
Brand: Renesas
SKU: ISL6225CA
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: ISL6225CA

Manufacturer:: Renesas

Category:: Special Purpose Regulators

Package:: 28-SSOP (0.154", 3.90mm Width)

Datasheet:: ISL6225CA.pdf

Description:: IC REG CTRL DDR DRAM 2OUT 28SSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,099

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

ISL6225CA from Intersil is a dual-channel synchronous buck PWM controller optimized for DDR memory power delivery and dual-output DC/DC regulation in mobile computing systems. It delivers 0.9V–5.5V adjustable outputs, supports automatic CCM/hysteretic mode switching, provides VTT tracking and VDDQ/2 reference generation, and operates with 300kHz fixed-frequency or diode-emulation light-load operation - enabling high-efficiency power conversion in notebook PCs and PDAs.

For engineers reviewing the ISL6225CA datasheet, ISL6225CA pinout, ISL6225CA application, or ISL6225CA equivalent, key selection considerations include its DDR-specific tracking architecture (VTT = VDDQ/2), dual independent PGOOD signals (or single PGOOD in DDR mode), phase-shifted channel operation (0°/90°/180°), MOSFET rDS(ON)-based current sensing, and integrated soft-start with 5µA ramp current.

Technical Context

The ISL6225CA implements voltage-feed-forward average current-mode control with internal compensation, eliminating external loop components. Its dual PWM channels use independent gate drivers with adaptive dead-time control and support three-phase relationships (0°, 90°, 180°) selected dynamically based on VIN and DDR pin state.

In DDR mode (DDR = HIGH), CH2 transforms into a bidirectional VTT supply tracking VDDQ/2, while PG2/REF becomes a buffered 1.0V reference output (±1% accuracy, 10mA drive). The IC integrates overvoltage protection (115% setpoint), undervoltage lockout (75% setpoint), and adjustable overcurrent protection using either MOSFET rDS(ON) or external sense resistors.

Key Specifications

Parameter	Value and Actual Design Meaning
Switching Frequency	300 kHz ±15% - enables compact magnetics and predictable EMI profile; frequency remains stable across input voltage range.
Output Voltage Range	0.9 V to 5.5 V per channel - set via external resistor divider; internal 0.9 V reference ensures tight regulation tolerance.
VDDQ/2 Reference Accuracy	±1% at 0–10 mA load - meets JEDEC DDR SDRAM VREF specification for reliable memory interface timing.
Overvoltage Threshold	110–130% of setpoint - clamps output by holding lower MOSFET ON; auto-resumes when decayed below threshold.
Soft-Start Ramp Current	5 µA - charges external capacitor to control output voltage rise time and limit inrush current during power-up.
Operating Temperature	–10°C to +85°C ambient - validated for mobile PC and PDA thermal environments without derating.
VCC Supply Range	+5.0 V ±5% - requires dedicated 5 V bias rail; includes UVLO with 4.35 V rising threshold and 4.35 V hysteresis.

Pinout & Package

ISL6225CA is housed in a 28-lead SSOP package (M28.15 footprint, 0.635 mm pitch) with exposed thermal pad for enhanced power dissipation in high-current applications.

Pin/Terminal	Circuit Role	Design Meaning
GND (1)	Signal ground reference	Common return for analog and digital circuitry; must be low-impedance connection to system ground plane.
LGATE1/LGATE2 (2,27)	Lower MOSFET gate drivers	Drive N-channel sync rectifiers; designed for fast turn-on/turn-off with 1.8–3 Ω pull-down resistance.
PGND1/PGND2 (3,26)	Power ground returns	Separate high-current paths for lower MOSFET sources; critical for minimizing noise coupling between channels.
PHASE1/PHASE2 (4,25)	Switch-node connections	Connect to junction of upper MOSFET source, inductor, and lower MOSFET drain; high dv/dt node requiring short trace routing.
UGATE1/UGATE2 (5,24)	Upper MOSFET gate drivers	Bootstrap-driven high-side outputs; support 33 V max boot-to-phase differential for wide VIN compatibility.
BOOT1/BOOT2 (6,23)	Bootstrap supply inputs	Connect to bootstrap capacitor-diode network; supplies floating gate drive for upper MOSFETs.
ISEN1/ISEN2 (7,22)	Current sense inputs	Monitor voltage drop across lower MOSFET rDS(ON); configurable for precision sensing with external resistor.
EN1/EN2 (8,21)	Channel enable inputs	Logic-level control: <0.8 V disables, >2.5 V enables; tied together for coordinated startup/shutdown.
VOUT1/VOUT2 (9,20)	Mode-select feedback inputs	Ground = forced CCM; connect to output = automatic CCM/hysteretic transition; enables smooth mode switching.
VSEN1/VSEN2 (10,19)	Voltage feedback inputs	Connect to resistor divider midpoint; used for regulation, PGOOD, OVP, and UVP detection with 80 nA bias current.
OCSET1/OCSET2 (11,18)	Overcurrent threshold setters	Resistor-to-ground sets trip point; OCSET2 repurposed as VTT tracking input in DDR mode.
SOFT1/SOFT2 (12,17)	Soft-start ramp inputs	5 µA internal current charges external capacitor; controls output voltage ramp rate and inrush limiting.
DDR (13)	DDR mode select input	HIGH activates DDR configuration: VTT tracking, VDDQ/2 reference on PG2/REF, and 0° channel synchronization.
VIN (14)	Feed-forward input	Provides input voltage to ramp generator; grounded in dual-step designs to double ramp slew rate and reduce jitter.
VCC (28)	Bias supply input	+5 V ±5% required; powers all internal circuits; includes UVLO with 4.35 V threshold and hysteresis.
PG1 (15)	CH1 power-good output	Open-drain signal asserted when VOUT1 is within ±10% of setpoint; requires external pull-up resistor.
PG2/REF (16)	Dual-function pin	In dual mode: PGOOD2 open-drain output; in DDR mode: VDDQ/2 buffered reference (0.99–1.01 × VDDQ/2).

Key Features

Feature	Design Value
Automatic CCM/hysteretic mode switching	Eliminates manual mode selection; improves light-load efficiency by >15% vs. fixed-frequency operation alone.
VTT bidirectional current sourcing/sinking	Supports DDR memory termination requirements with active pull-up/pull-down capability up to ±1 A.
VDDQ/2 buffered reference generation	Delivers stable 1.0 V reference (±1%) with 10 mA drive strength - meets JEDEC DDR-266/333 specifications.
rDS(ON)-based current sensing	Removes need for external sense resistor; reduces BOM cost and PCB area while maintaining ±10% OCP accuracy.
Programmable channel phase relationship	0° (DDR), 90° (low-interference DDR), or 180° (low-input-ripple dual supply) - selected automatically by VIN and DDR state.

Applications

DDR Memory Power Supply	Graphic Chipset Dual-Rail Supply
Use Scenario: Powering DDR SDRAM modules in notebook PCs requiring precise VDDQ and VTT rails with tight tracking. IC Role / Device Role / Timing Role: ISL6225CA acts as complete DDR power controller: CH1 regulates VDDQ (1.8 V or 2.5 V), CH2 generates VTT (VDDQ/2) with bidirectional current capability, and PG2/REF supplies buffered VREF. Use Value: Eliminates need for discrete op-amps or dedicated DDR PMICs; achieves ±1% VTT tracking accuracy and 100 ns response to VDDQ transients.	Use Scenario: Providing independent, tightly regulated 1.2 V core and 2.5 V I/O voltages for GPU or chipset in sub-notebook platforms. IC Role / Device Role / Timing Role: ISL6225CA operates in dual-channel mode with 180° phase shift to minimize input capacitor ripple current and reduce EMI. Use Value: Enables single-chip solution for two critical rails; reduces total solution size by 35% vs. discrete controllers and improves transient response by 40%.
Mobile PC Battery-to-Load Conversion	Handheld Instrument Dual-Output Supply
Use Scenario: Converting 5–24 V battery input directly to 1.5 V CPU core and 3.3 V peripheral rails in desknote systems. IC Role / Device Role / Timing Role: ISL6225CA functions as primary buck controller with VIN-connected feed-forward ramp, supporting wide input range and fast line regulation. Use Value: Maintains <±2% load regulation across 0–5 A load range and 5–24 V input; eliminates need for pre-regulator stage.	Use Scenario: Powering mixed-signal instrumentation with isolated analog (3.3 V) and digital (1.8 V) domains from a single Li-ion cell pack. IC Role / Device Role / Timing Role: ISL6225CA delivers independent, low-noise outputs with separate soft-start and PGOOD monitoring per channel. Use Value: Ensures sequenced power-up with <10 ms inter-rail delay; prevents latch-up during cold start and supports brown-out recovery.

DDR Memory Power Supply

Graphic Chipset Dual-Rail Supply

Use Scenario: Powering DDR SDRAM modules in notebook PCs requiring precise VDDQ and VTT rails with tight tracking.

IC Role / Device Role / Timing Role: ISL6225CA acts as complete DDR power controller: CH1 regulates VDDQ (1.8 V or 2.5 V), CH2 generates VTT (VDDQ/2) with bidirectional current capability, and PG2/REF supplies buffered VREF.

Use Value: Eliminates need for discrete op-amps or dedicated DDR PMICs; achieves ±1% VTT tracking accuracy and 100 ns response to VDDQ transients.

Use Scenario: Providing independent, tightly regulated 1.2 V core and 2.5 V I/O voltages for GPU or chipset in sub-notebook platforms.

IC Role / Device Role / Timing Role: ISL6225CA operates in dual-channel mode with 180° phase shift to minimize input capacitor ripple current and reduce EMI.

Use Value: Enables single-chip solution for two critical rails; reduces total solution size by 35% vs. discrete controllers and improves transient response by 40%.

Mobile PC Battery-to-Load Conversion

Handheld Instrument Dual-Output Supply

Use Scenario: Converting 5–24 V battery input directly to 1.5 V CPU core and 3.3 V peripheral rails in desknote systems.

IC Role / Device Role / Timing Role: ISL6225CA functions as primary buck controller with VIN-connected feed-forward ramp, supporting wide input range and fast line regulation.

Use Value: Maintains <±2% load regulation across 0–5 A load range and 5–24 V input; eliminates need for pre-regulator stage.

Use Scenario: Powering mixed-signal instrumentation with isolated analog (3.3 V) and digital (1.8 V) domains from a single Li-ion cell pack.

IC Role / Device Role / Timing Role: ISL6225CA delivers independent, low-noise outputs with separate soft-start and PGOOD monitoring per channel.

Use Value: Ensures sequenced power-up with <10 ms inter-rail delay; prevents latch-up during cold start and supports brown-out recovery.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual PWM controller applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ISL6227	Successor with improved thermal performance, extended VIN range (up to 28 V), and enhanced DDR reference accuracy (±0.5%).	Designed for newer DDR2/DDR3 platforms; supports higher VDDQ slew rates and tighter VTT tracking specs.	Preferred for new designs targeting DDR2+ compliance and longer product lifecycle; pin-compatible but requires updated layout for thermal pad.
RT8205A	Single-chip dual PWM with integrated MOSFET drivers only; lacks DDR-specific features (VTT tracking, VDDQ/2 buffer, PG2/REF dual function).	Suitable for generic dual-output applications but not DDR memory systems; no VTT sourcing/sinking capability.	Valid alternative where DDR functionality is unused; lower BOM cost but requires external op-amp for VTT if needed.

Compared with ISL6225CA, ISL6227 offers superior DDR timing margin and thermal headroom for high-density layouts, while RT8205A provides cost-effective dual regulation without DDR-specific circuitry - making ISL6225CA the optimal choice for legacy DDR SDRAM implementations requiring full JEDEC-compliant power delivery.

Availability

ISL6225CA is available at Aetrix Electronics and suitable for mobile PCs, PDAs, and handheld portable instruments requiring stable component supply and long-term industrial availability.

Supply support for ISL6225CA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Intersil Corporation (now part of Renesas Electronics) is a U.S.-based analog and power management IC designer known for high-performance power solutions in computing and communications.

The ISL6225CA belongs to Intersil's mobile power management portfolio, engineered specifically for DDR DRAM, SDRAM, and graphics chipset power delivery in space-constrained, battery-sensitive platforms.

FAQ

What is the maximum input voltage supported by the ISL6225CA?

The ISL6225CA supports an absolute maximum input voltage (VIN) of +27.0 V, with recommended operation from +5.0 V to +24.0 V. This wide range allows direct connection to notebook battery packs or unregulated intermediate rails. Exceeding 27.0 V risks permanent damage per Absolute Maximum Ratings. The device also accepts 3.3 V or 5 V system rails as input sources when configured for dual-step conversion.

How does the ISL6225CA implement DDR memory power delivery?

The ISL6225CA implements DDR power delivery by asserting the DDR pin HIGH, which reconfigures CH2 to track VDDQ/2, enables bidirectional current sourcing/sinking on VOUT2, and converts PG2/REF into a buffered VDDQ/2 reference output (0.99–1.01 × VDDQ/2). In this mode, channel synchronization shifts to 0° phase alignment to minimize interference between VDDQ and VTT switching edges - meeting JEDEC DDR timing requirements.

Can the ISL6225CA operate without external current sense resistors?

Yes, the ISL6225CA can operate without external current sense resistors by using the rDS(ON) of the lower MOSFETs for overcurrent protection and current-mode control. The ISEN pins monitor the voltage drop across the MOSFETs' on-resistance, eliminating the need for discrete sense resistors. An external resistor may be added to OCSET pins only when higher OCP precision is required beyond the ±10% typical accuracy of rDS(ON)-based sensing.

What is the purpose of the VOUT1 and VOUT2 pins on the ISL6225CA?

The VOUT1 and VOUT2 pins on the ISL6225CA determine operating mode: grounding them forces continuous conduction mode (FCCM) at all loads, while connecting them to their respective output voltages enables automatic CCM/hysteretic mode switching. This dual function simplifies design by allowing seamless transition between high-efficiency light-load operation and stable heavy-load regulation without additional control logic.

Does the ISL6225CA provide independent power-good signaling for both channels?

Yes, the ISL6225CA provides independent PGOOD signaling in dual-channel mode: PG1 indicates CH1 status and PG2/REF (configured as PGOOD2) indicates CH2 status - each asserting low when its output deviates >±10% from the setpoint after soft-start completion. In DDR mode, only PG1 remains active as PGOOD, while PG2/REF becomes the VDDQ/2 reference output - a deliberate functional trade-off to support DDR memory interface requirements.

ISL6225CA Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: 28-SSOP (0.154", 3.90mm Width)

Packaging:: Tube

Product Status:: Obsolete

Applications:: Controller, DDR DRAM, SDRAM

Voltage - Input:: 5V ~ 24V

Number of Outputs:: 2

Voltage - Output:: 0.9V ~ 5.5V

Operating Temperature:: -10°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 28-SSOP/QSOP

ISL6225CA FAQ

1.How can I place an order for ISL6225CA through Aetrix?

Please submit a Request for Quotation (RFQ) for ISL6225CA on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ISL6225CA reliable?

The price and inventory of ISL6225CA are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6225CA is usually 5 days.

3.What payment methods are accepted for ISL6225CA?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6225CA transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ISL6225CA?

ISL6225CA orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ISL6225CA order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ISL6225CA?

For technical support, including ISL6225CA datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6225CA requirements.

6.How does Aetrix verify that ISL6225CA is sourced from the original manufacturer or authorized distributors?

All ISL6225CA products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6225CA meets industry standards.

7.What is the process for return or replacement of ISL6225CA?

All ISL6225CA units undergo pre-shipment inspection (PSI). If there is an issue with ISL6225CA, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ISL6225CA part is unused and in its original packaging.

Return procedure for ISL6225CA:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…