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Renesas ISL6225CAZ-T

Part No.:
ISL6225CAZ-T
Manufacturer:
Renesas
Category:
Special Purpose Regulators
Package:
28-SSOP (0.154", 3.90mm Width)
Datasheet:
AetrixISL6225CAZ-T.pdf
Description:
IC REG CTRL DDR DRAM 2OUT 28SSOP
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:1,713

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Product details

Overview

ISL6225CAZ-T from Renesas (formerly Intersil) is a dual-channel synchronous buck PWM controller optimized for DDR memory power delivery and dual-output DC/DC conversion in mobile computing systems. It delivers 0.9V–5.5V adjustable outputs, supports 5V–24V input, operates at 300 kHz nominal switching frequency, and enables VTT tracking of VDDQ/2 in DDR mode - deployed in notebook PCs, PDAs, and graphic chipset power rails.

For engineers reviewing the ISL6225CAZ-T datasheet, ISL6225CAZ-T pinout, ISL6225CAZ-T application, or ISL6225CAZ-T equivalent, key selection considerations include its dual-mode operation (independent regulation vs. DDR-specific VTT/VREF generation), MOSFET rDS(ON)-based current sensing, 0°/90°/180° channel phase control, and integrated overvoltage/undervoltage protection with ±10% PGOOD thresholds.

Technical Context

The ISL6225CAZ-T implements average current-mode control with voltage feed-forward ramp modulation to maintain stable loop response across wide VIN (5V–24V) and load transients. Its dual PWM channels support independent soft-start, programmable overcurrent thresholds via OCSET pins, and adaptive dead-time gate drivers with 8Ω typical upper/lower pull-up resistance.

In DDR mode (DDR pin high), CH2 reconfigures as a bidirectional VTT sink/source tracking VDDQ/2, while PG2/REF becomes a buffered 1.0V reference output capable of sourcing up to 16 mA. Channel synchronization shifts from 180° out-of-phase (standard dual supply) to 0° in-phase (DDR mode) or 90° (VIN grounded + DDR high) to minimize inter-channel interference.

Key Specifications

Parameter Value and Actual Design Meaning
Switching Frequency 300 kHz ±15% - fixed-frequency CCM operation ensures predictable EMI profile and simplifies filter design.
Output Voltage Range 0.9V to 5.5V per channel - set by external resistive divider; internal 0.9V reference enables precise low-voltage regulation for DDR DRAM and SDRAM.
Input Voltage Range 5.0V to 24.0V - supports direct battery input (e.g., Li-ion packs) or system rail operation without auxiliary bias converters.
VTT Tracking Accuracy VTT = VDDQ/2 ±1% - achieved via buffered reference output (PG2/REF) and OCSET2 feedback in DDR mode.
Overvoltage Protection 115% of set point - holds lower MOSFET on and upper off until decay below threshold, preventing DDR memory damage.
Undervoltage Lockout 75% of set point - latches shutdown if output drops below threshold post-soft-start, ensuring clean reset behavior.
Soft-Start Time Programmable via external capacitor on SOFT1/SOFT2 - 5 µA internal current source enables controlled ramp-up and fault-safe test modes.

Pinout & Package

ISL6225CAZ-T is housed in a Pb-free 28-lead SSOP package (M28.15), 5.6 mm × 10.2 mm body size, 0.635 mm pitch, with exposed thermal pad (not electrically connected). Pin 1 is GND; pin 28 is VCC. Thermal resistance θJA = 78°C/W.

Pin/Terminal Circuit Role Design Meaning
GND (1) Signal ground reference Common return for analog and digital circuitry; must be low-impedance connection to PCB ground plane.
LGATE1 (2), LGATE2 (27) Lower MOSFET gate driver outputs Drive sources of synchronous rectifiers; designed for fast turn-on/turn-off with 1.8Ω typical pull-down resistance.
PGND1 (3), PGND2 (26) Power ground returns Low-inductance paths to lower MOSFET sources; separate from signal GND to avoid noise coupling into control loops.
PHASE1 (4), PHASE2 (25) Switch node connections Junction of upper MOSFET source, inductor, and lower MOSFET drain; critical for layout to minimize ringing and EMI.
UGATE1 (5), UGATE2 (24) Upper MOSFET gate driver outputs Bootstrap-driven high-side drivers; require external bootstrap diode/capacitor network referenced to BOOTx pins.
BOOT1 (6), BOOT2 (23) Bootstrap supply inputs Provide floating supply for upper gate drivers; connect to bootstrap capacitor anode and VCC via diode cathode.
ISEN1 (7), ISEN2 (22) Current sense inputs Monitor rDS(ON) voltage drop across lower MOSFETs; optional external sense resistor supported for precision OCP.
EN1 (8), EN2 (21) Channel enable inputs Active-high logic; both must be high for operation; tied together in standard designs to ensure synchronized startup.
VOUT1 (9), VOUT2 (20) Output voltage feedback points Connect to converter outputs to enable automatic CCM/hysteretic mode transition; ground to force FCCM operation.
VSEN1 (10), VSEN2 (19) Feedback voltage inputs Accept resistive divider output to set regulated voltage; also used for PGOOD, OVP, and UVP detection circuits.
OCSET1 (11), OCSET2 (18) Overcurrent threshold programming Resistor-to-ground sets current limit; in DDR mode, OCSET2 configures VTT tracking ratio and reference level.
SOFT1 (12), SOFT2 (17) Soft-start timing inputs Capacitor-to-ground sets ramp time; internal 5 µA current source charges cap to control output voltage slew rate.
DDR (13) DDR mode select input High = enable DDR configuration (VTT tracking, VDDQ/2 reference, 0° phase sync); low = independent dual-channel mode.
VIN (14) Feed-forward input Provides input voltage to ramp generator; grounded in dual-step systems to double ramp slope and reduce jitter.
VCC (28) Bias supply input +5.0V ±5% required; UVLO triggers at 4.3V (rising) / 4.1V (falling); powers all internal circuitry including gate drivers.
PG1 (15) CH1 Power-Good output Open-drain signal asserted when VOUT1 is within ±10% of set point; requires external pull-up to VCC or system rail.
PG2/REF (16) Dual-function pin In dual mode: PGOOD2 open-drain output; in DDR mode: buffered VDDQ/2 reference output (0.99–1.01×VOC2, 10 mA capable).

Key Features

Feature Design Value
Hysteretic light-load mode with diode emulation Automatically switches to variable-frequency operation below critical inductor current, improving efficiency >20% at <10% load without external components.
rDS(ON)-based current sensing Eliminates need for dedicated current-sense resistors; reduces BOM cost and board space while maintaining ±10% OCP accuracy across temperature.
Configurable channel phase relationship Supports 0° (DDR), 90° (low-interference DDR), or 180° (input ripple reduction) PWM alignment - selected automatically based on VIN and DDR state.
Integrated DDR memory power solution Generates VTT (bidirectional sink/source), VDDQ/2 reference, and coordinated PGOOD signaling - meets JEDEC DDR SDRAM specification requirements.
Internal feedback compensation Removes need for external Type II/III compensation networks; achieves >60° phase margin with standard ceramic output capacitors and typical PCB layout.

Applications

DDR Memory Power Supply Graphic Chipset Core Voltage

Use Scenario: Powering DDR2 SDRAM modules in ultraportable notebooks requiring tight VDDQ/VTT tracking and low-noise operation.

IC Role / Device Role / Timing Role: Dual-channel controller operating in DDR mode, generating VDDQ (1.8V) and VTT (0.9V) with 0° phase sync and buffered VDDQ/2 reference.

Use Value: Eliminates need for discrete tracking LDO and reference IC, reducing component count by ≥3 parts while meeting ±1% VTT regulation spec.

Use Scenario: Delivering core voltage (1.2V @ 15A) and I/O voltage (2.5V @ 3A) to GPU in sub-notebook platforms with shared battery input.

IC Role / Device Role / Timing Role: Independent dual-buck controller with 180° phase shift, enabling single-input dual-output regulation with minimized input capacitor RMS current.

Use Value: Reduces input ripple by ~70% versus in-phase operation, allowing smaller 10µF ceramic input caps instead of 47µF tantalum.

Mobile PC System Rail Generator Handheld Instrument Dual Supply

Use Scenario: Generating 3.3V system rail and 1.5V logic supply from 12V Li-ion battery in convertible tablet PCs.

IC Role / Device Role / Timing Role: Dual-channel buck controller with VIN-referenced feed-forward and adaptive dead-time gate drivers for wide-input stability.

Use Value: Maintains ±1% output regulation across full 5V–24V input range and 0–10A load step, eliminating need for post-regulation LDOs.

Use Scenario: Providing isolated 5.0V analog supply and 3.3V digital supply in battery-powered handheld oscilloscopes.

IC Role / Device Role / Timing Role: Dual-output controller with independent soft-start (SOFT1/SOFT2) and separate PGOOD signals for sequenced power-up.

Use Value: Enables reliable cold-start from depleted batteries (≥5V) with no external bias supply, reducing standby current to <30 µA.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel PWM controller applications.

Alternative Part Technical Difference Application Difference Selection Advice
ISL6227 Successor device with enhanced thermal performance (θJA = 65°C/W), wider VIN range (4.5V–28V), and improved light-load efficiency via optimized hysteretic comparator. Designed for newer mobile platforms requiring higher input voltage tolerance and lower quiescent current (<2.0 mA vs. 3.2 mA). Select ISL6227 for new designs targeting extended battery life and compatibility with 24V automotive-derived supplies.
RT8205A Single-chip dual-phase controller with integrated MOSFET drivers but no DDR-specific VTT/VREF generation; lacks PG2/REF pin functionality and OCSET2 tracking capability. Suitable for generic dual-output applications but cannot replace ISL6225CAZ-T in DDR memory subsystems without adding external tracking circuitry. Choose RT8205A only for non-DDR dual-rail systems where VTT tracking and buffered reference are not required.

Compared with ISL6225CAZ-T, ISL6227 offers superior thermal metrics and broader input range for next-gen mobile designs, while RT8205A provides cost-effective dual-phase control but requires external components to replicate DDR-specific functions - making ISL6225CAZ-T irreplaceable in legacy DDR memory power applications.

Availability

ISL6225CAZ-T is available at Aetrix Electronics and suitable for notebook PC motherboard designs, DDR memory module power systems, and portable graphics subsystems requiring stable component supply and long-term industrial availability.

Supply support for ISL6225CAZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation acquired Intersil in 2017 and maintains full technical and supply chain support for legacy Intersil power management ICs including the ISL6225 family.

The ISL6225 product line was engineered specifically for high-efficiency, compact dual-output power delivery in space-constrained mobile computing platforms - emphasizing DDR compliance, battery-input robustness, and minimal external component count.

FAQ

What is the recommended input voltage range for reliable operation of the ISL6225CAZ-T?

The ISL6225CAZ-T operates reliably with input voltages from +5.0V to +24.0V. It supports direct connection to Li-ion battery packs (typically 7.4V–12.6V) or system rails such as +5V or +12V. The VCC pin requires a regulated +5.0V ±5% supply derived from VIN or an auxiliary source - this bias rail must exceed 4.3V to exit UVLO and initiate soft-start.

How does the ISL6225CAZ-T implement VTT tracking in DDR memory applications?

In DDR mode (DDR pin high), the ISL6225CAZ-T configures CH2 to track VDDQ/2 using the PG2/REF pin as a buffered reference output. OCSET2 connects to the center of a resistive divider from VDDQ, setting the tracking ratio. The CH2 output actively sinks and sources current to maintain VTT within ±1% of VDDQ/2 - essential for DDR SDRAM termination compliance.

Can the ISL6225CAZ-T operate without external current-sense resistors?

Yes. The ISL6225CAZ-T uses the rDS(ON) of the lower MOSFETs for current sensing and overcurrent protection, eliminating the need for external sense resistors in most applications. An optional external resistor may be added at ISEN1/ISEN2 for higher precision OCP, but it is not required for basic functionality or JEDEC-compliant DDR operation.

What phase relationship is used between CH1 and CH2 in DDR mode, and how is it controlled?

In DDR mode (DDR = high), the ISL6225CAZ-T defaults to 0° phase alignment between CH1 and CH2 to minimize inter-channel interference during VDDQ/VTT transitions. If VIN is grounded while DDR is high, the controller switches to 90° phase shift - a configuration documented in the datasheet to further reduce crosstalk in sensitive DDR layouts.

Is the ISL6225CAZ-T still recommended for new designs, and what is its replacement?

No - the ISL6225CAZ-T is marked "NOT RECOMMENDED FOR NEW DESIGNS" in the official datasheet. Renesas recommends the ISL6227 as the direct functional successor, offering improved thermal performance, extended input voltage range (4.5V–28V), and enhanced light-load efficiency while maintaining pin compatibility and similar feature set for DDR and dual-rail applications.

ISL6225CAZ-T Specifications

Product attributes
Attribute value
Manufacturer:
Renesas
Series:
-
Package/Case:
28-SSOP (0.154", 3.90mm Width)
Packaging:
Tape & Reel (TR)
Product Status:
Obsolete
Applications:
Controller, DDR DRAM, SDRAM
Voltage - Input:
5V ~ 24V
Number of Outputs:
2
Voltage - Output:
0.9V ~ 5.5V
Operating Temperature:
-10°C ~ 85°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
28-SSOP/QSOP

ISL6225CAZ-T FAQ

1.How can I place an order for ISL6225CAZ-T through Aetrix?

Please submit a Request for Quotation (RFQ) for ISL6225CAZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ISL6225CAZ-T reliable?

The price and inventory of ISL6225CAZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6225CAZ-T is usually 5 days.

3.What payment methods are accepted for ISL6225CAZ-T?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6225CAZ-T transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ISL6225CAZ-T?

ISL6225CAZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ISL6225CAZ-T order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ISL6225CAZ-T?

For technical support, including ISL6225CAZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6225CAZ-T requirements.

6.How does Aetrix verify that ISL6225CAZ-T is sourced from the original manufacturer or authorized distributors?

All ISL6225CAZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6225CAZ-T meets industry standards.

7.What is the process for return or replacement of ISL6225CAZ-T?

All ISL6225CAZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL6225CAZ-T, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ISL6225CAZ-T part is unused and in its original packaging.

Return procedure for ISL6225CAZ-T:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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