Renesas ISL6265AHRTZ
- Part No.:
- ISL6265AHRTZ
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
ISL6265AHRTZ.pdf
- Description:
- IC REG CTRLR AMD 3OUT 48TQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL6265AHRTZ from Renesas (formerly Intersil) is a multi-output voltage regulator controller with integrated MOSFET drivers for AMD SVI-capable mobile CPUs. It delivers three independent regulated outputs - dual-core (VDD0/VDD1) and Northbridge (VDDNB) - supporting both uniplane two-phase and dual-plane single-phase configurations, 0.5% system accuracy over temperature, R3 Technology™ modulator for fast transient response, and operates across -10°C to +100°C ambient.
For engineers reviewing the ISL6265AHRTZ datasheet, ISL6265AHRTZ pinout, ISL6265AHRTZ application, or ISL6265AHRTZ equivalent, this page provides verified technical context, confirmed pin functions, real-world application scenarios for AMD mobile platforms, and validated alternative parts for design continuity and supply resilience.
Technical Context
The ISL6265AHRTZ implements Intersil's patented R3 Technology™ modulator, synthesizing inductor ripple current to enable variable-frequency hysteretic control while retaining error amplifier-based precision regulation. Its core modulator dynamically adjusts switching frequency during load transients - increasing frequency under step-load conditions to reduce output voltage deviation.
All three outputs feature differential remote sensing (VSEN/RTN), lossless current sensing (DCR for core, rDS(ON) for NB), and independent protection circuitry including overvoltage (1.77–1.82 V), undervoltage (240–350 mV), and overcurrent thresholds. The Serial VID Interface supports high-speed I²C-compatible SVI protocol with 12.5 mV steps across 0.500 V–1.55 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Configuration | Three independent controllers: dual-core (VDD0/VDD1) + Northbridge (VDDNB); supports uniplane two-phase or dual-plane single-phase operation |
| Voltage Range (SVI) | 0.500 V to 1.55 V in 12.5 mV steps - enables precise dynamic CPU voltage scaling per AMD SVI spec |
| System Accuracy | ±0.5% over temperature (0.75–1.55 V range); ±5 mV (0.50–0.7375 V) - ensures tight regulation for mobile CPU power integrity |
| Switching Frequency | 200–500 kHz programmable per channel - allows optimization of efficiency, size, and EMI for each rail |
| Gate Drive Capability | 2 A source/sink per UGATE/LGATE - drives high-side and low-side MOSFETs directly without external drivers |
| Protection Features | Per-rail OVP (1.77–1.82 V), UVP (240–350 mV), OCP - prevents damage during fault conditions with sub-250 µs PGOOD fault response |
| Operating Temp | -10°C to +100°C ambient - qualified for extended thermal envelope of mobile computing platforms |
Pinout & Package
ISL6265AHRTZ is housed in a Pb-free 48-lead 6 mm × 6 mm TQFN package (L48.6x6) with exposed thermal pad. Pin assignment is validated per FN6884 Rev 0.00 datasheet, Page 9 (Functional Pin Description) and Page 1 (Top View Pinout).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, PVCC, GND | Bias & gate drive supplies / reference ground | VCC powers control logic (5 V ±5%); PVCC powers gate drivers (5 V); GND connects to thermal pad for thermal and electrical reference |
| ENABLE, PWROK, SVC, SVD | Digital interface and enable control | ENABLE activates controller; PWROK gates SVI operation; SVC/SVD form two-wire SVI bus for dynamic VID programming |
| FB0/FB1/FB_NB, VSEN0/RTN0/VSEN1/RTN1/VSEN_NB/RTN_NB | Feedback and remote sense inputs | FB pins connect to resistor dividers; VSEN/RTN pairs provide differential die-voltage sensing per AMD spec to eliminate PCB IR drop error |
| UGATE0/UGATE1/UGATE_NB, LGATE0/LGATE1/LGATE_NB | Integrated MOSFET gate drivers | Each pair drives high-side and low-side FETs; 2 A drive strength supports fast switching with minimal external components |
| OCSET, OCSET_NB, RBIAS, OFS/VFIXEN | Configuration and protection setup | RBIAS sets internal references (117 kΩ to GND); OCSET/OCSET_NB set current-limit thresholds; OFS/VFIXEN selects SVI/VFIX mode and enables droop |
Key Features
| Feature | Design Value |
|---|---|
| R3 Technology™ modulator | Hybrid PWM/hysteretic architecture delivering faster transient response than fixed-frequency PWM while maintaining 0.5% DC accuracy |
| Dual-plane vs uniplane configuration | Auto-configured via RTN1 pin state at power-up - eliminates firmware dependency and enables motherboard-level flexibility |
| Differential remote sensing (VSEN/RTN) | Compensates for PCB trace resistance to regulate voltage precisely at CPU die - required by AMD mobile CPU specifications |
| Lossless current sensing | Core uses inductor DCR; Northbridge uses MOSFET rDS(ON) - eliminates sense resistor power loss and board area |
| PSI_L support with phase shedding | Enables automatic phase disable and DCM-mode entry during light load - improves efficiency in low-power states |
| Programmable soft-start & VID-on-the-fly | 2 mV/µs ramp rate for stable startup; 5–10 mV/µs dynamic VID adjustment - prevents overshoot and supports runtime voltage scaling |
Applications
| AMD Mobile Dual-Plane CPU Power | AMD Mobile Uniplane CPU Power |
|---|---|
|
Use Scenario: Motherboard powering dual-core AMD mobile processors (e.g., Turion X2, Athlon Neo) requiring separate VDD0 and VDD1 rails plus VDDNB. IC Role / Device Role / Timing Role: ISL6265AHRTZ acts as primary multi-rail VR controller, managing independent feedback loops, current balancing, and SVI communication with CPU. Use Value: Enables full compliance with AMD SVI specification while reducing component count via integrated gate drivers and lossless sensing. |
Use Scenario: Notebook platform using uniplane AMD CPU (e.g., Sempron M100, Athlon II Neo) where VDD0/VDD1 are internally merged. IC Role / Device Role / Timing Role: ISL6265AHRTZ configures CORE_0/CORE_1 as interleaved two-phase buck converter, doubling effective ripple frequency. Use Value: Reduces output capacitor count and size by 30–50% versus single-phase design, lowering BOM cost and PCB area. |
| Northbridge Voltage Regulation | Mobile Platform Power Sequencing |
|
Use Scenario: Regulating VDDNB for AMD chipset northbridge in thin-and-light notebooks where space and thermal constraints limit discrete solutions. IC Role / Device Role / Timing Role: ISL6265AHRTZ dedicates its third channel to VDDNB with rDS(ON) current sensing and independent OVP/UVP. Use Value: Eliminates need for separate NB controller IC, simplifying layout and improving timing alignment between core and NB rails. |
Use Scenario: Coordinating power-up sequence across CPU core, NB, and system rails in AMD-based embedded or ruggedized mobile systems. IC Role / Device Role / Timing Role: ISL6265AHRTZ uses PWROK input to gate SVI activation and synchronizes PGOOD assertion across all outputs. Use Value: Ensures deterministic power sequencing per AMD guidelines, preventing boot failures due to out-of-spec voltage timing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-output CPU voltage regulator controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6266HRTZ | Same pinout, enhanced SVI timing, improved PSI_L latency, and tighter 0.3% core accuracy (vs. 0.5%) | Required for newer AMD K10/K10.5 mobile CPUs with stricter SVI timing and lower voltage tolerance | Select ISL6266HRTZ when upgrading to post-2010 AMD mobile platforms or when tighter regulation is mandatory |
| RT8802AGQW | 48-pin QFN, supports SVI2, adds digital telemetry (I²C readback), but lacks R3 modulator and has fixed 300 kHz frequency | Suitable for designs needing voltage/current/temperature telemetry, but not for legacy AMD SVI-only systems requiring R3 transient performance | Choose RT8802AGQW only if telemetry and SVI2 compatibility are prioritized over transient response and backward SVI support |
Compared with ISL6265AHRTZ, ISL6266HRTZ offers higher accuracy and updated timing for newer AMD CPUs, while RT8802AGQW trades R3 responsiveness for telemetry and SVI2 - making ISL6265AHRTZ optimal for cost-sensitive, legacy AMD mobile designs requiring proven transient behavior and SVI1 compliance.
Availability
ISL6265AHRTZ is available at Aetrix Electronics and suitable for AMD mobile CPU power delivery, notebook motherboard VRMs, and embedded mobile computing platforms requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.
Supply support for ISL6265AHRTZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics acquired Intersil in 2017 and maintains full product support, documentation, and qualification for legacy Intersil power management ICs including the ISL6265A family.
The ISL6265A product line was designed specifically for AMD mobile CPU voltage regulation, delivering multi-rail control, SVI interface compliance, and R3 Technology™ for high-efficiency, low-noise power delivery in space-constrained notebooks.
FAQ
What is the operating temperature range for the ISL6265AHRTZ?
The ISL6265AHRTZ is rated for -10°C to +100°C ambient operating temperature, with junction temperature limits up to +125°C. This range meets the thermal requirements of mobile computing platforms including ultrabooks and embedded fanless systems where sustained high-temperature operation is common. All electrical specifications in the FN6884 datasheet are guaranteed across this full range.
How does the ISL6265AHRTZ configure itself for uniplane vs dual-plane CPU operation?
The ISL6265AHRTZ detects the CPU plane configuration at power-up via the RTN1 pin: if RTN1 is pulled low before ENABLE, it configures CORE_0 and CORE_1 as independent single-phase regulators for dual-plane CPUs; if RTN1 is pulled high (e.g., to +1.8V), it configures them as an interleaved two-phase regulator for uniplane CPUs. This hardware-based auto-detection eliminates firmware dependencies and ensures robust boot behavior.
Does the ISL6265AHRTZ support AMD SVI2 or only SVI1?
The ISL6265AHRTZ supports only AMD SVI1 (Serial VID Interface version 1), as confirmed by its datasheet FN6884, which specifies "Serial VID Interface (SVI)" with two-wire clock/data, 12.5 mV steps, and pre-PWROK metal VID codes. It does not implement SVI2 features such as bidirectional data, extended command sets, or telemetry readback - those require newer controllers like ISL6266 or RT8802A.
What is the purpose of the RBIAS pin on the ISL6265AHRTZ?
The RBIAS pin on the ISL6265AHRTZ requires a 117 kΩ resistor to GND to set internal reference currents for accurate current sensing and protection thresholds. Deviation from this value affects OCSET_NB trip point and system accuracy. Adding capacitance to RBIAS is strictly prohibited, as it introduces instability and can cause oscillation or erratic OCP behavior per datasheet warning on Page 9.
Can the ISL6265AHRTZ be used without the Serial VID Interface?
Yes - the ISL6265AHRTZ supports VFIX mode when OFS/VFIXEN is pulled to +3.3V, allowing fixed output voltages determined by SVC/SVD states at power-up (e.g., 0.8–1.1 V per Table 1). In this mode, SVI communication is disabled, enabling use in non-AMD or simplified systems where dynamic voltage scaling is unnecessary and fixed rail voltages suffice.
ISL6265AHRTZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- Robust Ripple Regulator™ (R3)
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- Controller, AMD SVI Capable Mobile CPU
- Voltage - Input:
- 5V ~ 24V
- Number of Outputs:
- 3
- Voltage - Output:
- 0.5V ~ 1.55V
- Operating Temperature:
- -10°C ~ 100°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-TQFN (6x6)
ISL6265AHRTZ FAQ
1.How can I place an order for ISL6265AHRTZ through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6265AHRTZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6265AHRTZ reliable?
The price and inventory of ISL6265AHRTZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6265AHRTZ is usually 5 days.
3.What payment methods are accepted for ISL6265AHRTZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6265AHRTZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6265AHRTZ?
ISL6265AHRTZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6265AHRTZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6265AHRTZ?
For technical support, including ISL6265AHRTZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6265AHRTZ requirements.
6.How does Aetrix verify that ISL6265AHRTZ is sourced from the original manufacturer or authorized distributors?
All ISL6265AHRTZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6265AHRTZ meets industry standards.
7.What is the process for return or replacement of ISL6265AHRTZ?
All ISL6265AHRTZ units undergo pre-shipment inspection (PSI). If there is an issue with ISL6265AHRTZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6265AHRTZ part is unused and in its original packaging.
Return procedure for ISL6265AHRTZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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