Renesas ISL6310CRZ-T
- Part No.:
- ISL6310CRZ-T
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
ISL6310CRZ-T.pdf
- Description:
- IC REG CTRLR DDR 1OUT 32QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL6310CRZ-T from Renesas (formerly Intersil) is a two-phase buck PWM controller IC with integrated high-current MOSFET drivers, designed for precision voltage regulation in high-current, low-voltage point-of-load applications. It supports 1- or 2-phase operation, delivers ±0.5% system accuracy at 1.2V/1.5V output, uses combined DCR and rDS(ON) current sensing for load-line droop and channel balancing, and operates up to 1.5MHz per phase - enabling compact, thermally efficient DC/DC converters for DDR memory and FPGA core supplies.
For engineers reviewing the ISL6310CRZ-T datasheet, ISL6310CRZ-T pinout, ISL6310CRZ-T application, or ISL6310CRZ-T equivalent, key selection considerations include its dual-phase interleaved timing control, differential remote voltage sensing with ±0.8% accuracy at 0.6V/0.9V, programmable DAC reference (0.6V/0.9V/1.2V/1.5V), lossless rDS(ON)-based current sharing, and integrated overvoltage/overcurrent protection with OVP pin for crowbar implementation.
Technical Context
The ISL6310CRZ-T implements a two-phase interleaved PWM architecture with adaptive non-overlap timing (10ns UGATE/LGATE turn-on dead time) and a shared sawtooth oscillator synchronized across phases. Its error amplifier features 96dB DC gain and 20MHz GBW, supporting Type II/III compensation via external R-C networks on FB/COMP pins.
Current sensing combines continuous inductor DCR monitoring (for load-line droop and overcurrent protection) with cycle-by-cycle rDS(ON) sampling (for precise channel-current balance), both referenced to IREF/ISUM/ICOMP nodes. The controller supports pre-biased start-up, digital soft-start, and dynamic reference selection via REF0/REF1 logic inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Count | Configurable 1- or 2-phase operation via 2PH pin; enables interleaved switching for reduced ripple and thermal spreading. |
| Output Voltage Accuracy | ±0.5% over temperature at 1.2V/1.5V DAC settings; ensures tight regulation for sensitive FPGA/ASIC cores. |
| Switching Frequency | Up to 1.5MHz per phase (set by FS-to-GND resistor); allows small magnetics and high transient response. |
| Gate Drive Capability | Integrated drivers with 0.85–2.0Ω lower-source/sink resistance (PVCC = 12V); directly drives high-side/lower MOSFETs without external buffers. |
| Current Sensing Method | Simultaneous DCR (for droop & OCP) and rDS(ON) (for channel balance); eliminates need for separate sense resistors or ICs. |
| Remote Sensing | Differential VSEN/RGND input with 20MHz bandwidth and 55µA bias current; compensates PCB IR drop for accurate load-point regulation. |
| Protection Features | OVP (DAC +125–175mV), UVP (82% DAC), thermal shutdown (160°C), open-sense-line detection, and shoot-through prevention. |
Pinout & Package
ISL6310CRZ-T is housed in a RoHS-compliant 32-lead 5mm × 5mm QFN package (L32.5x5) with exposed thermal pad. Pin count, layout, and thermal resistance (θJA = 35°C/W, θJC = 5°C/W) are optimized for high-power density board layouts requiring efficient heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (3) | Bias supply input | +5V ±5% supply for internal logic and error amp; requires local 1.0µF ceramic decoupling. |
| PVCC (15) | Power gate drive supply | +5V to +12V input for MOSFET drivers; sets gate voltage swing and drive strength. |
| REF0/REF1 (30,21) | DAC reference select | 2-bit TTL inputs selecting fixed DAC reference: 0.6V/0.9V/1.2V/1.5V; internally pulled to ~1.2V. |
| ISEN1/ISEN2 (26,16) | rDS(ON) current sense inputs | Connect to PHASE node via RISEN; enable per-channel current sampling for real-time balance correction. |
| ISUM/ICOMP/IREF (12,10,13) | DCR current sense interface | Form summing node (ISUM), output (ICOMP), and reference (IREF) for droop voltage generation and OCP threshold setting. |
| UGATE1/LGATE1 (25,27) | Channel 1 upper/lower gate drivers | Direct-drive outputs for synchronous buck high-side/low-side MOSFETs; no external gate resistors recommended. |
| PHASE1/PHASE2 (23,19) | High-side source return | Return path for upper MOSFET gate drive; must be connected to respective PHASE node for bootstrap operation. |
| VSEN/RGND (8,7) | Remote voltage sense inputs | Differential pair connected to load sense points; rejects common-mode noise and PCB voltage drop. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated dual-phase PWM + gate drivers | Reduces BOM count by eliminating discrete driver ICs and simplifies layout for space-constrained VRMs. |
| Dual current sensing (DCR + rDS(ON)) | Enables simultaneous load-line droop control and <1% channel current imbalance without added power loss. |
| Differential remote sensing with 20MHz BW | Maintains ±0.5% regulation accuracy despite >100mV PCB IR drop between regulator and load. |
| Programmable DAC reference (4 values) | Allows single-part support of multiple output voltages (0.6V–1.5V) without changing external components. |
| Pre-biased soft-start capability | Permits safe startup into powered loads (e.g., hot-plugged modules) without output voltage overshoot. |
Applications
| DDR Memory Core Regulator | FPGA/ASIC Core Supply |
|---|---|
Use Scenario: Regulating 1.2V/1.5V core voltage for DDR3/DDR4 memory subsystems with fast load transients up to 50A/µs. IC Role / Device Role / Timing Role: Two-phase buck controller managing interleaved switching, current sharing, and droop-based voltage positioning to meet JEDEC VDDQ tolerance. Use Value: Achieves <±15mV output deviation under 30A step load via combined DCR/rDS(ON) sensing and 1.5MHz switching. | Use Scenario: Powering high-performance FPGA or ASIC core rails requiring stable sub-1.5V supplies with tight DC accuracy and thermal derating. IC Role / Device Role / Timing Role: Precision voltage regulator implementing remote sensing, digital soft-start, and overtemperature shutdown to protect silicon die during configuration and operation. Use Value: Delivers ±0.5% system accuracy over –40°C to +85°C ambient while supporting pre-biased startup for partial reconfiguration. |
| Chipset Voltage Regulator | Low-Voltage Server VRM |
Use Scenario: Generating 0.9V–1.2V supply for CPU chipset I/O or memory controller with high efficiency and minimal footprint. IC Role / Device Role / Timing Role: Dual-phase controller using 2PH pin configuration and external reference input to match chipset VID requirements. Use Value: Enables <90% peak efficiency at 40A with 5×5mm QFN package and integrated drivers - reducing solution size by 35% vs. discrete controller+driver designs. | Use Scenario: High-reliability, multi-rail server power delivery where long-term stability and fault containment are critical. IC Role / Device Role / Timing Role: Primary VRM controller providing OVP/UVP, PGOOD signaling, and OVP pin-driven crowbar protection for downstream logic. Use Value: Prevents catastrophic failure during overvoltage events via fast clamp action (<100ns) and dedicated OVP output driving external SCR/MOSFET. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar two-phase buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IR35201MTRPBF | Supports 3/4-phase operation; includes PMBus interface and digital telemetry; higher pin count (40-QFN); requires external EEPROM for configuration. | Targeted at digitally managed server VRMs requiring telemetry, margining, and dynamic VID updates - not drop-in compatible. | Select when digital control, fault logging, or multi-rail coordination is required; ISL6310CRZ-T remains optimal for analog-controlled, cost-sensitive designs. |
| TPS53632RGTR | Single-chip 3-phase controller with integrated drivers; supports up to 60A; uses D-CAP3 control; no DAC reference selection - relies on external resistor divider or PMBus. | Optimized for high-current notebook/server CPUs; lacks dual-reference DAC and rDS(ON) current balance mode of ISL6310CRZ-T. | Choose for higher phase count and integrated D-CAP3 loop response; ISL6310CRZ-T preferred where DAC flexibility and analog simplicity are prioritized. |
Compared with IR35201MTRPBF and TPS53632RGTR, the ISL6310CRZ-T offers unique analog configurability via REF0/REF1 DAC selection and combined DCR/rDS(ON) sensing - making it ideal for fixed-function, high-accuracy analog VRMs where digital overhead is unnecessary.
Availability
ISL6310CRZ-T is available at Aetrix Electronics and suitable for high-current DDR memory regulators, FPGA/ASIC core supplies, and low-voltage chipset power applications requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.
Supply support for ISL6310CRZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation (acquired Intersil in 2017) is a global semiconductor leader delivering microcontrollers, analog power, and SoC solutions for automotive, industrial, and computing markets.
The ISL6310CRZ-T belongs to Renesas' legacy Intersil multiphase buck controller product line, engineered specifically for high-efficiency, low-voltage point-of-load regulation in memory and logic power systems.
FAQ
What is the operating temperature range for the ISL6310CRZ-T?
The ISL6310CRZ-T is rated for an ambient operating temperature range of 0°C to +70°C, as specified in the Intersil FN9209 datasheet. This commercial-grade rating aligns with its intended use in non-extended-environment applications such as desktop motherboards and embedded computing platforms. Thermal shutdown activates at 160°C junction temperature, with recovery at 100°C.
How does the ISL6310CRZ-T implement current balancing between phases?
The ISL6310CRZ-T achieves channel current balance using lossless rDS(ON) sensing on each lower MOSFET during conduction, sampled every switching cycle. The sampled currents are compared to the average channel current (IAVG), and pulse-width corrections are applied in real time via the error amplifier's modified VCOMP signal - ensuring <1% imbalance across load conditions without external current-sense resistors.
Can the ISL6310CRZ-T operate with an external voltage reference?
Yes, the ISL6310CRZ-T supports external reference input via the REF pin. When an external reference (0.6V–1.75V) is applied directly to REF, the internal DAC is disabled, and regulation targets that voltage. The DAC pin must remain unconnected in this configuration. This mode enables custom output voltages beyond the four DAC presets while retaining all other control functions.
What is the purpose of the DROOP pin on the ISL6310CRZ-T?
The DROOP pin on the ISL6310CRZ-T enables or disables load-line (droop) voltage positioning. Tying DROOP to ICOMP activates droop, generating a voltage proportional to load current that is summed into VDIFF to achieve intentional output voltage sag under load - improving transient response and current sharing in multi-phase systems. Connecting DROOP to IREF disables this function.
Does the ISL6310CRZ-T support pre-biased load startup?
Yes, the ISL6310CRZ-T is explicitly designed to support start-up into a pre-biased output. Its digital soft-start circuitry monitors the FB/VDIFF voltage and initiates ramping only after detecting a valid initial condition, preventing reverse current flow and output voltage overshoot - a critical feature for hot-swap and modular power architectures where the output rail may already be energized.
ISL6310CRZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Controller, DDR
- Voltage - Input:
- 5V ~ 12V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.6V ~ 2.3V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-QFN (5x5)
ISL6310CRZ-T FAQ
1.How can I place an order for ISL6310CRZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6310CRZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6310CRZ-T reliable?
The price and inventory of ISL6310CRZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6310CRZ-T is usually 5 days.
3.What payment methods are accepted for ISL6310CRZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6310CRZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6310CRZ-T?
ISL6310CRZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6310CRZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6310CRZ-T?
For technical support, including ISL6310CRZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6310CRZ-T requirements.
6.How does Aetrix verify that ISL6310CRZ-T is sourced from the original manufacturer or authorized distributors?
All ISL6310CRZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6310CRZ-T meets industry standards.
7.What is the process for return or replacement of ISL6310CRZ-T?
All ISL6310CRZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL6310CRZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6310CRZ-T part is unused and in its original packaging.
Return procedure for ISL6310CRZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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