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Renesas ISL6323ACRZR5381
- Part No.:
- ISL6323ACRZR5381
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
ISL6323ACRZR5381.pdf
- Description:
- IC REG CTRLR AMD SVI 2OUT 48QFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,988
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Product details
Overview
ISL6323ACRZR5381 from Renesas Electronics (formerly Intersil) is a monolithic dual PWM hybrid controller for AMD SVI/PVI split-plane and uniplane processors. It delivers precision core voltage regulation via 2–4-phase synchronous buck conversion and independent Northbridge (VDDNB) regulation via single-phase PWM, supporting ±0.6% system accuracy, droop-based load line programming, and adaptive phase alignment. It powers high-performance desktop/server CPU power delivery systems requiring tight transient response and multi-phase channel balancing.
For engineers reviewing the ISL6323ACRZR5381 datasheet, ISL6323ACRZR5381 pinout, ISL6323ACRZR5381 application, or ISL6323ACRZR5381 equivalent, key selection considerations include SVI/PVI interface mode configuration, integrated vs. external driver support (2-phase internal / 3–4-phase external), DCR-based current sensing architecture, selectable switching frequency up to 1 MHz, and dual-rail power-good signaling for VDD/VDDNB monitoring.
Technical Context
The ISL6323ACRZR5381 implements two independent control loops: a multi-phase VR controller (2–4 phases) for VDD core with fully differential continuous DCR current sensing, APA, and dual-edge modulation; and a single-phase VR controller for VDDNB with matching remote sensing and ±0.6% accuracy. Both sections share serial VID (SVI) or parallel VID (PVI) interface decoding, simultaneous digital soft-start, and programmable gate drive bias (5–12 V).
Its hybrid architecture enables dynamic phase shedding via PSI_L, supports load-line droop for bulk capacitor reduction, and integrates upper/lower MOSFET drivers for the core section while allowing external driver expansion. The controller uses adaptive shoot-through protection, variable ramp-based APP modulation, and independent overvoltage/undervoltage thresholds per rail.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Output Configuration | 2–4-phase synchronous buck VR controller with integrated drivers for first two phases; PWM3/PWM4 support external drivers for 3rd/4th phase |
| Northbridge Output | Single-phase synchronous buck VR controller with integrated driver and dedicated current sense (ISEN_NB±) |
| VID Interface Modes | Configurable SVI (2-wire clock/data) or PVI (6-bit parallel); mode selected by VID1/SEL state prior to EN assertion |
| System Accuracy | ±0.6% over temperature for VDD >1.000V; ±1.0% for 0.600–1.000V; supports offset calibration via OFS pin |
| Switching Frequency | Selectable 80 kHz to 1 MHz via FS resistor; droop enabled when FS tied to GND, disabled when tied to VCC |
| Current Sensing | Fully differential, continuous DCR sensing on all channels (ISEN1±–ISEN4±, ISEN_NB±); enables precise load line and channel balancing |
| Protection Features | Multi-tier OVP (1.73–1.84 V trip), UVLO (VSEN −270 to −325 mV), per-rail PWROK, and adaptive shoot-through prevention |
Pinout & Package
ISL6323ACRZR5381 is housed in a 48-lead 7×7 mm QFN package (L48.7x7) with exposed thermal pad. Pin functions are validated per FN6878.0 datasheet Rev. 0, including dual-purpose VID/SVI pins (VID0/VFIXEN, VID2/SVD, VID3/SVC), dedicated core/NB sensing (VSEN/RGND, FB_NB/COMP_NB), and independent gate drive blocks (UGATE1/LGATE1/BOOT1/PVCC1_2 and UGATE_NB/LGATE_NB/BOOT_NB/PVCC_NB).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VID1/SEL | Mode selection input | Latched at EN rising edge to configure SVI (LO) or PVI (HI); determines function of VID0/VFIXEN, VID2/SVD, VID3/SVC |
| VSEN & RGND | Core remote sense inputs | Differential pair connected to processor VDDFB[H,L]; enables precision regulation independent of PCB IR drop |
| ISEN1±–ISEN4± | Core phase current sense | Four differential pairs for DCR-based current measurement; used for droop, balancing, and OCP |
| ISEN_NB± | Northbridge current sense | Differential pair for VDDNB current sensing; enables NB-side load line and overcurrent protection |
| UGATE1, LGATE1, BOOT1, PVCC1_2 | Core Phase 1 gate drive | Integrated high/low-side driver outputs with bootstrap supply; supports 5–12 V gate bias |
| UGATE_NB, LGATE_NB, BOOT_NB, PVCC_NB | Northbridge gate drive | Independent integrated driver for VDDNB; separate bias and sensing from core section |
| PWROK & VDDPWRGD | Power-good status outputs | PWROK indicates SVI protocol status; VDDPWRGD is open-drain signal low if either rail exceeds OVP/UVP limits |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive Phase Alignment (APA) | Adjustable trip level via APA-to-COMP resistor; dynamically aligns phase timing to minimize output ripple during transients |
| Active Pulse Positioning (APP) Modulation | Enables sub-cycle response to di/dt load steps by placing PWM edges anywhere within switching period-no fixed dead-time penalty |
| Phase Shedding via PSI_L | Drops active core phases from 2/3/4 to 1 under light load, reducing switching losses without compromising regulation stability |
| Dual Independent Soft-Start | Simultaneous digital soft-start for both VDD and VDDNB rails ensures coordinated ramp-up and avoids sequencing conflicts |
| Programmable Gate Drive Bias | PVCC1_2 and PVCC_NB accept 5–12 V supplies; allows optimization of Rds(on) vs. switching loss trade-off for different MOSFETs |
Applications
| Desktop CPU Power Delivery | Server Processor VRM |
|---|---|
Use Scenario: High-current core voltage regulation for AMD Phenom II or Athlon II processors in ATX desktop motherboards. IC Role / Device Role / Timing Role: Dual-rail PWM controller managing VDD (2–4 phase) and VDDNB (1-phase) with SVI interface and real-time VID updates. Use Value: Enables <1% output deviation under 20 A/µs load steps via APA and APP modulation, reducing bulk capacitance by 30% versus fixed-frequency controllers. | Use Scenario: Multi-socket server motherboard delivering stable 1.1–1.35 V core and 1.0–1.2 V Northbridge voltages to AMD Opteron processors. IC Role / Device Role / Timing Role: Primary VR controller implementing PVI mode for legacy compatibility and dual-rail power-good signaling for system-level fault isolation. Use Value: Supports phase shedding and droop programming to meet 80 PLUS Titanium efficiency requirements at 10–100% load range. |
| Workstation Graphics Platform | Embedded Computing Module |
Use Scenario: Compact workstation board powering AMD FirePro GPUs with tightly coupled CPU/GPU voltage domains. IC Role / Device Role / Timing Role: Hybrid controller using SVI interface to coordinate core and NB voltages with GPU VRMs via shared clock/data bus. Use Value: Differential remote sensing (VSEN/RGND, FB_NB/COMP_NB) eliminates layout-induced regulation error across 6-layer PCBs with >100 mm trace lengths. | Use Scenario: Industrial embedded system requiring long-lifecycle, RoHS-compliant CPU power with thermal derating support. IC Role / Device Role / Timing Role: Single-chip solution providing both core and NB regulation with −40°C to +85°C operation (ISL6323AIRZ variant), though ISL6323ACRZR5381 rated 0°C to +70°C. Use Value: Integrated drivers reduce BOM count by 8 MOSFET drivers versus discrete controller+driver solutions, saving 12 mm² PCB area. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-rail CPU voltage regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6323AIRZ | Identical functionality and pinout; extended temperature range (−40°C to +85°C) vs. ISL6323ACRZR5381 (0°C to +70°C) | Suitable for industrial/server environments requiring wider ambient operating range | Select ISL6323AIRZ when thermal margin or extended temp qualification is required; otherwise ISL6323ACRZR5381 suffices for commercial desktop use. |
| IR35201MTRPBF | Supports Intel VR12.5/VR12.6 protocols; lacks native AMD SVI support; uses digital SVID interface instead of analog SVI/PVI | Designed for Intel Core i-series platforms; incompatible with AMD VID encoding and droop programming model | Only consider IR35201MTRPBF for Intel-based designs; not a functional substitute for AMD-specific ISL6323ACRZR5381 applications. |
Compared with ISL6323AIRZ, ISL6323ACRZR5381 offers identical electrical performance but reduced thermal operating range-making it lower-cost for commercial desktops. Versus IR35201MTRPBF, ISL6323ACRZR5381 provides native AMD interface compliance and analog droop control, which are essential for legacy and cost-sensitive AMD platforms.
Availability
ISL6323ACRZR5381 is available at Aetrix Electronics and suitable for desktop motherboard design, server VRM development, and AMD processor evaluation platforms requiring stable component supply and full production traceability.
Supply support for ISL6323ACRZR5381 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and maintains full technical support and manufacturing continuity for legacy Intersil power management ICs.
The ISL6323ACRZR5381 belongs to Renesas' high-performance CPU voltage regulator controller product line, designed specifically for AMD processor power delivery with SVI/PVI interface compliance, multi-phase scalability, and precision analog regulation.
FAQ
What interface protocols does the ISL6323ACRZR5381 support?
The ISL6323ACRZR5381 supports both AMD Serial VID (SVI) and Parallel VID (PVI) interfaces. Mode selection is determined by the logic state of the VID1/SEL pin prior to enabling the EN signal: low selects SVI (two-wire clock/data bus conforming to AMD specifications), high selects PVI (6-bit parallel interface with 25 mV or 12.5 mV step resolution). The ISL6323ACRZR5381 decodes VID commands independently for core and Northbridge rails.
How does the ISL6323ACRZR5381 implement phase shedding for light-load efficiency?
The ISL6323ACRZR5381 implements phase shedding via the PSI_L signal, which triggers automatic reduction of active core phases from 2/3/4 down to 1 when load current drops below threshold. This reduces switching losses and gate drive power without disrupting regulation stability or requiring firmware intervention. The ISL6323ACRZR5381 maintains full droop programming and current sensing capability even in single-phase mode.
Can the ISL6323ACRZR5381 be used in both SVI and PVI modes on the same PCB design?
Yes-the ISL6323ACRZR5381 supports hardware-selectable SVI or PVI mode via the VID1/SEL pin. By routing this pin to a strapping resistor or system GPIO, a single PCB layout can accommodate both AMD processor families: SVI for newer CPUs (e.g., Phenom II) and PVI for legacy parts (e.g., Athlon 64 X2). The ISL6323ACRZR5381 latches the mode at EN assertion and retains it throughout operation.
What is the purpose of the OFS pin on the ISL6323ACRZR5381?
The OFS pin on the ISL6323ACRZR5381 provides programmable DC offset current (27.5–34.5 µA source or 50.5–56.5 µA sink) to generate a calibrated voltage offset between FB and VSEN. Connecting an external resistor from OFS to GND introduces negative offset; connecting to VCC introduces positive offset. This enables fine-tuning of core voltage setpoint to compensate for board-level tolerances or thermal drift-critical for meeting tight ±0.6% system accuracy specs across temperature.
Does the ISL6323ACRZR5381 integrate MOSFET drivers for both core and Northbridge outputs?
The ISL6323ACRZR5381 integrates full upper/lower MOSFET drivers for the first two core phases (UGATE1/LGATE1/BOOT1/PVCC1_2 and UGATE2/LGATE2/BOOT2) and for the Northbridge output (UGATE_NB/LGATE_NB/BOOT_NB/PVCC_NB). It does not integrate drivers for third/fourth core phases-those require external drivers connected to PWM3/PWM4 outputs. This hybrid integration balances BOM cost, layout flexibility, and thermal management.
ISL6323ACRZR5381 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, AMD SVI
- Voltage - Input:
- 5V ~ 12V
- Number of Outputs:
- 2
- Voltage - Output:
- Up to 2V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-QFN (7x7)
ISL6323ACRZR5381 FAQ
1.How can I place an order for ISL6323ACRZR5381 through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6323ACRZR5381 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6323ACRZR5381 reliable?
The price and inventory of ISL6323ACRZR5381 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6323ACRZR5381 is usually 5 days.
3.What payment methods are accepted for ISL6323ACRZR5381?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6323ACRZR5381 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6323ACRZR5381?
ISL6323ACRZR5381 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6323ACRZR5381 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6323ACRZR5381?
For technical support, including ISL6323ACRZR5381 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6323ACRZR5381 requirements.
6.How does Aetrix verify that ISL6323ACRZR5381 is sourced from the original manufacturer or authorized distributors?
All ISL6323ACRZR5381 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6323ACRZR5381 meets industry standards.
7.What is the process for return or replacement of ISL6323ACRZR5381?
All ISL6323ACRZR5381 units undergo pre-shipment inspection (PSI). If there is an issue with ISL6323ACRZR5381, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6323ACRZR5381 part is unused and in its original packaging.
Return procedure for ISL6323ACRZR5381:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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