Renesas ISL6323AIRZR5381
- Part No.:
- ISL6323AIRZR5381
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
ISL6323AIRZR5381.pdf
- Description:
- IC REG CTRLR AMD SVI 2OUT 48QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL6323AIRZR5381 from Renesas (formerly Intersil) is a monolithic dual PWM hybrid controller for AMD SVI/PVI split-plane and uniplane processors, delivering ±0.6% core voltage regulation accuracy, 2–4-phase multi-phase control for VDD core, and single-phase control for VDDNB, with integrated MOSFET drivers and differential remote sensing in a 48-lead QFN package.
For engineers reviewing the ISL6323AIRZR5381 datasheet, ISL6323AIRZR5381 pinout, ISL6323AIRZR5381 application, or ISL6323AIRZR5381 equivalent, key selection considerations include SVI/PVI interface mode selection, droop-enabled load-line programming, DCR-based current sensing, adaptive phase alignment (APA), and simultaneous digital soft-start of both outputs.
Technical Context
The ISL6323AIRZR5381 implements two independent PWM control loops: a 2–4-phase VR controller for AMD processor core voltage (VDD) with fully differential continuous DCR current sensing, APA, and dual-edge modulation; and a dedicated single-phase VR controller for Northbridge voltage (VDDNB) with matching ±0.6% system accuracy and differential remote sensing.
It supports dynamic mode switching via VID1/SEL latching at enable, enabling either SVI (2-wire serial) or PVI (6-bit parallel) interface operation - with full SVI compliance and VID voltage ranges of 0.375–1.55V in 12.5/25mV steps - while maintaining separate gate drive bias (5–12V) and independent overcurrent/overvoltage protection per channel.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating Temp Range | -40°C to +85°C - qualified for industrial-grade motherboard and server power delivery applications. |
| Core Voltage Accuracy | ±0.6% over temperature - enables tight regulation for high-performance AMD CPUs without external calibration. |
| Switching Frequency | Up to 1 MHz - selectable via FS resistor; supports high-density, low-inductance designs with reduced output ripple. |
| Current Sensing | Fully differential continuous DCR sensing - eliminates discrete sense resistors, improves thermal stability, and enables precise load-line droop. |
| Phase Support | 2–4-phase core + 1-phase NB - integrates drivers for 2-phase; supports 3/4-phase via PWM3/PWM4 outputs to external drivers. |
| Interface Modes | SVI (2-wire clock/data) and PVI (6-bit VID) - mode selected by VID1/SEL state prior to EN assertion; no runtime reconfiguration. |
| Protection Features | Multi-tier OVP/UVP, per-channel OCP, PSI_L phase shedding, shoot-through prevention - ensures robust fault handling in high-current CPU rails. |
Pinout & Package
ISL6323AIRZR5381 is housed in a 48-lead, 7 mm × 7 mm, 0.5 mm pitch QFN package with exposed thermal pad (PKG DWG # L48.7x7). Pin functions are validated per FN6878.0 datasheet Figure 1 (Top View) and Functional Pin Description (pp. 9–11).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VID1/SEL | Mode Selection Input | Latched at EN rising edge to select SVI (LO) or PVI (HI); determines function of VID0/VFIXEN, VID2/SVD, VID3/SVC pins. |
| VSEN / RGND | Differential Core Sense Inputs | Connect to CPU VDDFB[H,L] for precision remote sensing; enables ±0.6% regulation accuracy across temp/load. |
| ISEN1+ to ISEN4- | Multi-phase DCR Current Sense | Four differential pairs for per-phase current monitoring; required for channel balancing, droop, and OCP in 2–4-phase operation. |
| UGATE1/LGATE1, UGATE2/LGATE2 | Integrated Gate Drivers | Drive upper/lower MOSFETs directly for 2-phase core; support 5–12V gate bias via PVCC1_2. |
| PHASE_NB, UGATE_NB, LGATE_NB | Northbridge Driver Outputs | Independent single-phase driver set for VDDNB rail; uses PVCC_NB bias and ISEN_NB+/− for current sensing. |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive Phase Alignment (APA) | Adjustable trip level via external resistor on APA pin; dynamically aligns phase timing to minimize transient undershoot during high di/dt load steps. |
| Dual-Edge Modulation | Enables immediate PWM response to rapid load transients - reduces initial voltage dip without ringback artifacts common in traditional PWM schemes. |
| PSI_L Phase Shedding | Drops active phases to one under light load; maintains high efficiency without requiring external sequencing logic or firmware intervention. |
| Simultaneous Digital Soft-Start | Coordinated ramp-up of both core and NB outputs prevents sequencing conflicts and ensures stable power-up of AMD processor domains. |
| Variable Gate Drive Bias | PVCC1_2 and PVCC_NB independently configurable from 5V to 12V - optimizes Rds(on) vs. switching loss trade-off for diverse MOSFET selections. |
Applications
| AMD Socket AM3 Desktop Motherboard | AMD Socket C32 Server Platform |
|---|---|
Use Scenario: Power delivery for dual-core or quad-core AMD Phenom II processors with SVI interface and split-plane architecture. IC Role / Device Role / Timing Role: Dual PWM controller managing VDD core (2–4-phase) and VDDNB (1-phase) simultaneously; synchronizes soft-start and monitors PWROK for BIOS handoff. Use Value: Eliminates need for separate core/NB controllers; achieves ±0.6% regulation with integrated DCR sensing, reducing BOM count and PCB area by >30% vs. discrete solutions. | Use Scenario: High-reliability 1U/2U server board powering AMD Opteron 6100-series CPUs with PVI VID interface and uniplane VDD. IC Role / Device Role / Timing Role: Multi-phase VR controller for VDD only (PVI mode); disables NB regulator section; provides phase shedding via PSI_L for energy-efficient idle states. Use Value: Supports 6-bit VID decoding (0.375–1.55V @ 12.5/25mV steps) and 1MHz switching - enables compact, high-efficiency 12V-in/1.1V-out core rail with <1% total regulation error. |
| AMD Fusion APU Reference Design | Embedded Industrial Control Unit |
Use Scenario: Power management for early-generation AMD A-series APUs integrating CPU/GPU on single die with SVI protocol. IC Role / Device Role / Timing Role: Hybrid controller executing SVI handshake, driving core/NB rails with synchronized soft-start, and reporting PWROK to chipset upon valid voltage lock. Use Value: Fully compliant with AMD SVI spec; leverages APA and droop to meet stringent GPU load transient requirements (<500ns recovery) without external compensation. | Use Scenario: Fanless industrial PC using AMD G-Series SoC with extended temperature requirements (-40°C to +85°C). IC Role / Device Role / Timing Role: Industrial-grade dual VR controller operating across full temp range; uses differential sensing (VSEN/RGND, FB_NB/RGND_NB) to reject noise in electrically noisy environments. Use Value: Qualified to -40°C to +85°C; supports RoHS-compliant Pb-free + anneal finish; delivers stable core/NB regulation despite wide ambient swings and EMI exposure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output CPU voltage regulator controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6323ACRZ | 0°C to +70°C operating range; identical electrical specs and pinout. | Restricted to commercial-temperature computing platforms (e.g., standard ATX desktops). | Select ISL6323ACRZ only when ambient operating temperature remains within 0–70°C and industrial qualification is not required. |
| RT8803AZQW | Single-chip dual controller with integrated drivers; supports Intel IMVP-7, not AMD SVI/PVI; different VID encoding and phase control logic. | Designed for Intel Core i-series CPUs; incompatible with AMD SVI bus timing and PVI DAC mapping. | RT8803AZQW is not a functional substitute for ISL6323AIRZR5381 in AMD platforms due to protocol-level incompatibility. |
Compared with ISL6323ACRZ, the ISL6323AIRZR5381 adds industrial temperature support without sacrificing performance or pin compatibility; compared with RT8803AZQW, it provides native AMD interface compliance and SVI-specific features like VFIXEN and SVD/SVC signaling - making it irreplaceable in AMD-optimized designs.
Availability
ISL6323AIRZR5381 is available at Aetrix Electronics and suitable for AMD motherboard design, server power delivery, and embedded industrial control applications requiring stable component supply, long-lifecycle availability, and guaranteed RoHS-compliant sourcing.
Supply support for ISL6323AIRZR5381 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and maintains full technical and manufacturing continuity for legacy Intersil power management ICs including the ISL6323A family.
The ISL6323A product line was designed specifically for high-efficiency, space-constrained CPU voltage regulation in AMD-based platforms - emphasizing SVI/PVI interoperability, multi-phase scalability, and integrated driver consolidation.
FAQ
What interface protocols does the ISL6323AIRZR5381 support?
The ISL6323AIRZR5381 supports both AMD Serial VID (SVI) and Parallel VID (PVI) interfaces. Mode selection is determined by the logic state of the VID1/SEL pin prior to EN assertion: low selects SVI (two-wire clock/data), high selects PVI (6-bit VID input). The ISL6323AIRZR5381 implements full SVI compliance per AMD specifications and decodes PVI voltages from 0.375V to 1.55V in 12.5mV or 25mV steps.
How does the ISL6323AIRZR5381 achieve ±0.6% core voltage accuracy?
The ISL6323AIRZR5381 achieves ±0.6% system accuracy over temperature through differential remote voltage sensing (VSEN/RGND), precision internal DACs, and calibrated error amplifier offset. This specification is verified across -40°C to +85°C and includes contributions from VID DAC linearity, reference drift, and compensation network tolerance - all validated per FN6878.0 Electrical Specifications table on page 7.
Can the ISL6323AIRZR5381 operate in 4-phase mode for the core rail?
Yes, the ISL6323AIRZR5381 supports 2-, 3-, or 4-phase operation for the core voltage rail. It integrates drivers for two phases (UGATE1/LGATE1, UGATE2/LGATE2); additional phases are enabled by connecting PWM3 and PWM4 outputs to external drivers (e.g., ISL6610/ISL6612), while configuring unused ISEN− pins to +5V. The ISL6323AIRZR5381's channel detection logic automatically adapts to the active phase count.
What is the purpose of the APA pin on the ISL6323AIRZR5381?
On the ISL6323AIRZR5381, the APA (Adaptive Phase Alignment) pin sets the trip threshold and time constant for dynamic phase realignment during load transients. A 100µA internal current source flows into APA; connecting an external resistor from APA to COMP adjusts the alignment sensitivity. This feature minimizes output voltage undershoot during high di/dt load steps by proactively shifting PWM edges across phases - a capability confirmed in the ISL6323AIRZR5381 datasheet Figure 3 and "Active Pulse Positioning" section.
Does the ISL6323AIRZR5381 provide independent control of the Northbridge rail?
Yes, the ISL6323AIRZR5381 provides fully independent control of the Northbridge (VDDNB) rail via its dedicated single-phase PWM controller. It includes separate gate drivers (UGATE_NB/LGATE_NB), current sensing inputs (ISEN_NB+/−), error amplifier pins (FB_NB/COMP_NB), and remote sense return (RGND_NB). In PVI mode, the NB regulator is disabled - a hardware-enforced behavior documented in the ISL6323AIRZR5381 Typical Application schematic on page 5.
ISL6323AIRZR5381 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, AMD SVI
- Voltage - Input:
- 5V ~ 12V
- Number of Outputs:
- 2
- Voltage - Output:
- Up to 2V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-QFN (7x7)
ISL6323AIRZR5381 FAQ
1.How can I place an order for ISL6323AIRZR5381 through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6323AIRZR5381 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6323AIRZR5381 reliable?
The price and inventory of ISL6323AIRZR5381 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6323AIRZR5381 is usually 5 days.
3.What payment methods are accepted for ISL6323AIRZR5381?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6323AIRZR5381 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6323AIRZR5381?
ISL6323AIRZR5381 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6323AIRZR5381 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6323AIRZR5381?
For technical support, including ISL6323AIRZR5381 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6323AIRZR5381 requirements.
6.How does Aetrix verify that ISL6323AIRZR5381 is sourced from the original manufacturer or authorized distributors?
All ISL6323AIRZR5381 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6323AIRZR5381 meets industry standards.
7.What is the process for return or replacement of ISL6323AIRZR5381?
All ISL6323AIRZR5381 units undergo pre-shipment inspection (PSI). If there is an issue with ISL6323AIRZR5381, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6323AIRZR5381 part is unused and in its original packaging.
Return procedure for ISL6323AIRZR5381:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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