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Renesas ISL6323BIRZ-TR5381
- Part No.:
- ISL6323BIRZ-TR5381
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
ISL6323BIRZ-TR5381.pdf
- Description:
- IC REG CTRLR AMD SVI 2OUT 48QFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,336
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Product details
Overview
ISL6323BIRZ-TR5381 from Renesas Electronics (formerly Intersil) is a monolithic dual PWM hybrid controller for AMD SVI/PVI split-plane and uniplane processors. It delivers precision core voltage regulation via 2–4-phase synchronous buck conversion (±0.6% system accuracy), supports serial VID (SVI) and parallel VID (PVI) interfaces, and integrates drivers for both multi-phase VDD and single-phase VDDNB rails. It is used in high-performance desktop/server CPU power delivery.
For engineers reviewing the ISL6323BIRZ-TR5381 datasheet, ISL6323BIRZ-TR5381 pinout, ISL6323BIRZ-TR5381 application, or ISL6323BIRZ-TR5381 equivalent, key selection considerations include SVI/PVI mode flexibility, droop-based load-line programming, differential DCR current sensing, adaptive phase alignment (APA), and -40°C to +85°C industrial temperature operation.
Technical Context
The ISL6323BIRZ-TR5381 implements two independent control loops: a multi-phase VR controller (2–4 phases) for AMD processor core voltage with fully differential continuous DCR sensing, APA, and dual-edge modulation; and a single-phase VR controller for Northbridge (VDDNB) with identical sensing and regulation fidelity. Both sections support simultaneous digital soft-start and selectable switching frequency up to 1 MHz.
It features hybrid interface support - SVI mode uses two-wire clock/data bus compliant with AMD SVI specs, while PVI mode decodes 6-bit parallel VID inputs (0.375V–1.55V in 12.5/25mV steps). PSI_L-driven phase shedding reduces active phases to two under light load, improving efficiency without compromising transient response.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating Temp Range | -40°C to +85°C - qualified for industrial-grade motherboard and server board deployment. |
| Core Voltage Accuracy | ±0.6% over temperature - enables tight regulation of modern AMD CPU core voltages under dynamic load. |
| Switching Frequency | Up to 1 MHz - allows smaller magnetics and faster transient response in space-constrained VRMs. |
| VID Interface Support | AMD SVI (2-wire) and PVI (6-bit parallel) - provides backward/forward compatibility across AMD processor generations. |
| Droop Load-Line | Programmable via RSET - reduces bulk output capacitance requirements by enabling controlled voltage sag under load. |
| Current Sensing | Fully differential continuous DCR sensing - eliminates need for discrete sense resistors and improves channel current balance accuracy. |
| Phase Shedding | PSI_L-triggered reduction to 2-phase operation - maintains regulation integrity while cutting driver losses at light load. |
Pinout & Package
ISL6323BIRZ-TR5381 is housed in a 48-lead 7×7 mm QFN package (Pb-free, RoHS-compliant) with exposed thermal pad. Pin functions are validated per Intersil FN6879.0 datasheet Figure 1 (Top View).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VID1/SEL | Mode Selection Input | Latches SVI (low) or PVI (high) configuration at enable rising edge; determines function of VID0/VFIXEN, VID2/SVD, VID3/SVC pins. |
| ISEN1+ / ISEN1− to ISEN4+ / ISEN4− | Multi-phase DCR Sense Inputs | Enable fully differential, continuous current sensing per channel for load-line programming and precise phase balancing. |
| UGATE1/LGATE1, UGATE2/LGATE2 | Integrated Gate Drivers | Drive upper/lower MOSFETs directly in 2-phase mode; PWM3/PWM4 outputs support external drivers for 3-/4-phase expansion. |
| FB / COMP / VSEN / RGND | Core VR Feedback Loop | Supports remote-sense compensation networks; ±0.6% accuracy maintained via differential sensing and offset trimming (OFS pin). |
| PHASE_NB / UGATE_NB / LGATE_NB | Northbridge VR Outputs | Provide dedicated single-phase gate drive and sensing for VDDNB rail with identical regulation architecture as core VR. |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive Phase Alignment (APA) | Adjustable trip level via APA-to-COMP resistor - dynamically aligns phase timing to minimize output ripple during transients. |
| Active Pulse Positioning (APP) Modulation | Sub-cycle PWM edge placement - enables immediate response to high di/dt load steps without ringback artifacts. |
| Variable Gate Drive Bias (5–12V) | Separate PVCC1_2 and PVCC_NB supplies - optimizes FET switching loss vs. conduction loss trade-off per rail. |
| Dual-Tier Overvoltage Protection | Core OVP: VDAC + 225–275mV; System OVP: 1.73–1.84V - ensures robust fault containment for CPU and NB rails. |
| Simultaneous Digital Soft-Start | Independent ramp control for core and NB outputs - prevents inrush current conflict and ensures coordinated power-up sequencing. |
Applications
| Desktop CPU Power Delivery | Server Processor VRM |
|---|---|
Use Scenario: High-current, low-voltage core regulation for AMD Phenom II/X-series CPUs on ATX motherboards. IC Role / Device Role / Timing Role: Dual-loop PWM controller managing 4-phase VDD and 1-phase VDDNB with SVI interface and droop-based load line. Use Value: Enables <1% voltage deviation under 30A step load while reducing output capacitor count by 30% via programmable droop. | Use Scenario: Multi-socket server board delivering stable core/NB voltages to AMD Opteron processors with thermal margining. IC Role / Device Role / Timing Role: Industrial-temp (-40°C to +85°C) hybrid controller supporting PVI fallback and PSI_L phase shedding for energy-efficient idle states. Use Value: Maintains ±0.6% regulation accuracy across full temperature range and enables >15% efficiency gain at 20% load via 2-phase operation. |
| AMD Platform Reference Design | Embedded Computing Module |
Use Scenario: OEM reference board validation for AMD 700-series chipsets requiring SVI-compliant power sequencing. IC Role / Device Role / Timing Role: Primary VR controller implementing AMD SVI protocol handshake, PWROK assertion, and VDDPWRGD coordination. Use Value: Eliminates need for external SVI translator IC; reduces BOM count by integrating dual VR control, drivers, and interface logic. | Use Scenario: Compact embedded system (e.g., COM Express Type 6) powering AMD G-Series APUs in fanless industrial enclosures. IC Role / Device Role / Timing Role: Space-optimized 48-pin QFN solution delivering both core and NB rails with integrated drivers and thermal-pad-enhanced dissipation. Use Value: Reduces PCB area by 40% vs. discrete controller + dual driver solution while meeting IPC/JEDEC MSL3 reflow requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output CPU voltage regulator controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6323BCRZ | Same silicon, 0°C to +70°C temp grade; identical pinout and electrical specs. | Restricted to commercial-temperature desktop motherboards; not rated for extended thermal environments. | Select ISL6323BIRZ-TR5381 for industrial/server use; ISL6323BCRZ only where ambient stays within 0–70°C. |
| RT8803AZSP | Single-chip dual-controller with integrated MOSFET drivers; supports Intel IMVP-7, not AMD SVI/PVI. | Designed for Intel Core i-series CPUs; lacks SVI bus compliance and VID step resolution for AMD processors. | Not interchangeable - RT8803AZSP cannot decode AMD SVI commands or 6-bit PVI codes; requires different firmware and layout. |
Compared with ISL6323BCRZ, ISL6323BIRZ-TR5381 extends operational reliability to industrial temperatures without design change; compared with RT8803AZSP, it provides native AMD interface compliance and differential DCR sensing essential for accurate load-line implementation on AMD platforms.
Availability
ISL6323BIRZ-TR5381 is available at Aetrix Electronics and suitable for desktop motherboard design, server VRM development, and AMD platform reference designs requiring stable component supply and long-term industrial temperature support.
Supply support for ISL6323BIRZ-TR5381 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics acquired Intersil in 2017 and maintains full support for its high-performance analog and power management portfolio.
The ISL6323BIRZ-TR5381 belongs to Intersil's CPU voltage regulator controller product line, engineered specifically for AMD processor power delivery with SVI/PVI interface flexibility, multi-phase efficiency optimization, and industrial-grade thermal robustness.
FAQ
What interface protocols does the ISL6323BIRZ-TR5381 support?
The ISL6323BIRZ-TR5381 supports both AMD Serial VID (SVI) - a two-wire clock/data bus compliant with AMD specifications - and Parallel VID (PVI) - a 6-bit interface with 12.5 mV and 25 mV voltage steps across 0.375 V to 1.55 V. Mode selection is latched at EN pin rising edge via VID1/SEL pin state.
Does the ISL6323BIRZ-TR5381 integrate MOSFET drivers?
Yes, the ISL6323BIRZ-TR5381 integrates dual upper/lower gate drivers for two phases (UGATE1/LGATE1, UGATE2/LGATE2) and a dedicated single-phase driver set for Northbridge (UGATE_NB/LGATE_NB). For 3- or 4-phase core operation, PWM3/PWM4 outputs drive external drivers while internal drivers remain active for first two phases.
What is the purpose of the RSET pin on the ISL6323BIRZ-TR5381?
The RSET pin on the ISL6323BIRZ-TR5381 sets the effective value of internal current-sense resistors by connecting an external resistor to VCC. It enables programmable droop-based load-line regulation and supports thermal compensation using a PTC thermistor network to track inductor DCR drift over temperature.
How does the ISL6323BIRZ-TR5381 handle overcurrent protection?
The ISL6323BIRZ-TR5381 implements dual-tier overcurrent protection: average-channel OCP (87–120 µA trip, RSET = 28.2 kΩ) and individual-channel limiting (142 µA), plus dynamic VID-change thresholds. It also features multi-tiered overvoltage protection and undervoltage lockout on both core and NB rails with hysteresis.
Can the ISL6323BIRZ-TR5381 operate in both SVI and PVI modes simultaneously?
No - the ISL6323BIRZ-TR5381 operates exclusively in either SVI or PVI mode, selected at power-on by the logic state of the VID1/SEL pin prior to EN assertion. In SVI mode, VID0/VFIXEN, VID2/SVD, and VID3/SVC serve as SVI control signals; in PVI mode, those same pins become VID0–VID3 inputs alongside VID4 and VID5.
ISL6323BIRZ-TR5381 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Controller, AMD SVI
- Voltage - Input:
- 5V ~ 12V
- Number of Outputs:
- 2
- Voltage - Output:
- Up to 2V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-QFN (7x7)
ISL6323BIRZ-TR5381 FAQ
1.How can I place an order for ISL6323BIRZ-TR5381 through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6323BIRZ-TR5381 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6323BIRZ-TR5381 reliable?
The price and inventory of ISL6323BIRZ-TR5381 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6323BIRZ-TR5381 is usually 5 days.
3.What payment methods are accepted for ISL6323BIRZ-TR5381?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6323BIRZ-TR5381 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6323BIRZ-TR5381?
ISL6323BIRZ-TR5381 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6323BIRZ-TR5381 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6323BIRZ-TR5381?
For technical support, including ISL6323BIRZ-TR5381 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6323BIRZ-TR5381 requirements.
6.How does Aetrix verify that ISL6323BIRZ-TR5381 is sourced from the original manufacturer or authorized distributors?
All ISL6323BIRZ-TR5381 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6323BIRZ-TR5381 meets industry standards.
7.What is the process for return or replacement of ISL6323BIRZ-TR5381?
All ISL6323BIRZ-TR5381 units undergo pre-shipment inspection (PSI). If there is an issue with ISL6323BIRZ-TR5381, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6323BIRZ-TR5381 part is unused and in its original packaging.
Return procedure for ISL6323BIRZ-TR5381:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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