My Inquiry
My Account
Renesas ISL6324ACRZR5381
- Part No.:
- ISL6324ACRZR5381
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
ISL6324ACRZR5381.pdf
- Description:
- IC REG CTRLR AMD SVI 2OUT 48QFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,864
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ISL6324ACRZR5381 from Renesas (formerly Intersil) is a monolithic dual PWM hybrid controller for AMD SVI/PVI split-plane and uniplane processors, delivering ±0.5% system voltage regulation accuracy over temperature, supporting 2–4-phase core VR and single-phase North Bridge (VDDNB) regulation, with integrated MOSFET drivers and I²C programmability for voltage offset, OVP/PGOOD thresholds, and PSI_L phase shedding control in server and desktop CPU power delivery.
For engineers reviewing the ISL6324ACRZR5381 datasheet, ISL6324ACRZR5381 pinout, ISL6324ACRZR5381 application, or ISL6324ACRZR5381 equivalent, this page provides verified technical context on hybrid SVI/PVI mode operation, droop-based load line programming, differential DCR current sensing, adaptive phase alignment (APA), and dual-output transient response optimization - all critical for AMD processor VR design validation and BOM selection.
Technical Context
The ISL6324ACRZR5381 implements two independent PWM control loops: a multi-phase (2–4-phase) core regulator with fully differential continuous DCR current sensing, APA, and dual-edge modulation for high di/dt transient response; and a single-phase North Bridge regulator with identical sensing architecture and shared I²C interface. Both regulators support programmable output voltage offset, OVP/PGOOD trip levels, and PSI_L-triggered phase shedding with configurable cycle count.
SVI mode enables serial VID communication via SDA/SCL with AMD processors using SVC/SVD signals, while PVI mode decodes 6-bit parallel VID inputs (VID0–VID5); mode selection is latched at EN rising edge via VID1/SEL. Droop is enabled by connecting FS to GND (225–265 kHz typical), disabled by connecting FS to VCC (245–310 kHz typical), and supports up to 1 MHz switching frequency with external RT resistor.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Regulator Type | Dual-output monolithic PWM controller: 2–4-phase core VR + 1-phase NB VR |
| System Accuracy | ±0.5% over temperature for VDAC > 1.000V - ensures tight CPU core voltage tolerance under thermal stress |
| Switching Frequency | 225–265 kHz (droop enabled, FS→GND) or 245–310 kHz (droop disabled, FS→VCC); adjustable up to 1 MHz via RT resistor |
| Current Sensing | Fully differential, continuous DCR sensing on all 4 core phases and NB channel - enables precise load-line programming and per-channel current balancing |
| I²C Interface | Two-wire AMD-compliant interface for independent core/NB voltage margining, OVP/PGOOD threshold setting, and PSI_L state control |
| Phase Shedding | Programmable PSI_L-driven phase reduction (1–4 phases) with configurable entry/exit PWM cycle count - reduces light-load losses without firmware intervention |
| Gate Drive | Integrated drivers: UGATE/LGATE for core (PHASE1/PHASE2), NB (PHASE_NB); 1.25Ω lower sink resistance enables fast MOSFET turn-off for efficiency |
Pinout & Package
ISL6324ACRZR5381 is housed in a 48-lead 7×7 mm QFN package (Pb-free, exposed thermal pad) with 0.5 mm pitch. Pin functions are validated per FN6880.1 datasheet Rev. 1.0 (April 29, 2010).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VID1/SEL | Mode selection input | Latched at EN rising edge to configure SVI (low) or PVI (high) operation - determines function of VID0/VFIXEN, VID2/SVC, VID3/SVD pins |
| VSEN / RGND | Core remote sense pair | Differential input to precision error amplifier - connects directly to CPU VDDFB[H,L] for accurate core voltage regulation |
| ISEN1+ to ISEN4+, ISEN_NB+ | Current sense positive inputs | Connect to VCORE/VNB side of RC sense network - enables per-phase DCR current measurement for load line and balancing |
| ISEN1− to ISEN4−, ISEN_NB− | Current sense negative inputs | Connect to inductor-side node of RC sense network - forms differential pair with corresponding ISEN+ for noise-immune current sensing |
| UGATE1/2/NB, LGATE1/2/NB | Integrated gate drive outputs | Direct PWM outputs for upper/lower MOSFETs - eliminate need for external drivers in 2-phase core + NB configurations |
| SCL / SDA | I²C bidirectional interface | AMD-compliant serial bus for real-time voltage margining, fault threshold adjustment, and PSI_L state management |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive Phase Alignment (APA) | Configurable trip level via APA-to-COMP resistor - dynamically aligns phase timing to minimize output voltage dip during load transients |
| Dual-edge modulation | Enables immediate PWM turn-on within switching cycle - reduces initial response latency to high di/dt CPU load steps |
| Programmable droop | Output voltage decreases linearly with load current - allows reduction of bulk output capacitance while maintaining stability |
| Simultaneous digital soft-start | Coordinated ramp-up of both core and NB outputs - prevents sequencing violations and inrush current imbalance |
| Multi-tiered overvoltage protection | Independent OVP thresholds for core and NB, configurable via I²C - prevents CPU damage during regulation faults |
Applications
| Server CPU Power Delivery | Desktop AMD Platform VRM |
|---|---|
Use Scenario: High-current, multi-core AMD EPYC or Ryzen processors requiring tight core voltage regulation and dynamic phase management under variable workloads. IC Role / Device Role / Timing Role: Dual-output hybrid controller managing 4-phase VDD core and 1-phase VDDNB with SVI protocol handshake and I²C runtime tuning. Use Value: ±0.5% system accuracy and APA-driven transient response maintain CPU stability during rapid load changes in virtualized environments. |
Use Scenario: ATX motherboard VRM powering AMD AM4/AM5 CPUs with split-plane (core + NB) or uniplane configurations. IC Role / Device Role / Timing Role: Monolithic PWM controller implementing PVI mode for legacy VID decoding or SVI mode for modern serial interface compliance. Use Value: Integrated drivers and programmable PSI_L shedding reduce component count and improve light-load efficiency without sacrificing transient performance. |
| Workstation GPU Auxiliary Rail | Embedded x86 Compute Module |
Use Scenario: Secondary high-precision rail for GPU memory or I/O die voltage in dual-processor workstations. IC Role / Device Role / Timing Role: Single-phase NB regulator (VDDNB path) repurposed as independent auxiliary supply with I²C-adjustable voltage and OVP. Use Value: Independent I²C control of NB output enables fine-grained margining and fault threshold adaptation for non-CPU loads. |
Use Scenario: Space-constrained embedded systems using AMD Ryzen Embedded processors with strict thermal and layout constraints. IC Role / Device Role / Timing Role: Compact 7×7 mm QFN solution providing both core and NB regulation with minimal external components and no external drivers required for 2-phase operation. Use Value: Reduced BOM count and integrated thermal pad simplify thermal design and improve long-term reliability in fanless enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output CPU voltage regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6323IRZ | Single-output 3–4-phase controller without NB regulator or SVI interface - lacks I²C programmability and dual-rail capability | Only suitable for uniplane CPU cores; cannot support AMD split-plane architectures requiring independent VDDNB regulation | Select ISL6323IRZ only when NB rail is handled by separate IC or integrated into CPU package. |
| RT8802A | Single-chip dual-output controller with SVI2 support, but no PVI mode, no APA, and fixed 3-phase core topology - uses external current sense amplifiers | Compatible with newer AMD platforms using SVI2, but not backward-compatible with PVI or legacy SVI implementations | Choose RT8802A for new designs targeting AMD Ryzen 5000+ with SVI2, where APA and PVI are not required. |
Compared with ISL6324ACRZR5381, ISL6323IRZ omits NB regulation and I²C flexibility, limiting use to core-only applications, while RT8802A trades PVI compatibility and APA for SVI2 compliance and simplified layout - making ISL6324ACRZR5381 uniquely suited for mixed-mode AMD platform support across generations.
Availability
ISL6324ACRZR5381 is available at Aetrix Electronics and suitable for server motherboard development, AMD desktop platform VRM design, and embedded compute module power delivery requiring stable component supply, long-lifecycle availability, and RoHS-compliant packaging.
Supply support for ISL6324ACRZR5381 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics acquired Intersil in 2017 and maintains full product support, documentation, and qualification for legacy Intersil power management ICs including the ISL6324A family.
The ISL6324A product line was designed specifically for AMD processor power delivery, combining SVI/PVI interface flexibility, multi-phase core regulation, and integrated North Bridge control in a single monolithic IC to reduce VRM complexity and cost.
FAQ
What interface modes does the ISL6324ACRZR5381 support?
The ISL6324ACRZR5381 supports both AMD Serial VID (SVI) and Parallel VID (PVI) interfaces. Mode selection is determined by the logic level on VID1/SEL prior to EN assertion: low enables SVI mode (using SDA/SCL, SVC/SVD), high enables PVI mode (using VID0–VID5). This dual-mode capability allows backward and forward compatibility across AMD processor generations.
How does the ISL6324ACRZR5381 implement load-line programming?
The ISL6324ACRZR5381 implements droop-based load-line programming using fully differential, continuous DCR current sensing on all core phases and the NB channel. The sensed current modulates the reference voltage in real time, causing output voltage to decrease linearly with load - enabling reduced output capacitance while maintaining loop stability and transient response.
What is the purpose of the APA pin on the ISL6324ACRZR5381?
The APA (Adaptive Phase Alignment) pin on the ISL6324ACRZR5381 sets the trip threshold for dynamic phase timing adjustment. A resistor between APA and COMP configures the current threshold at which phase alignment shifts to minimize output voltage deviation during rapid load transients - a key feature for maintaining CPU stability under burst workloads.
Can the ISL6324ACRZR5381 operate with only the core regulator active?
Yes - in PVI mode, only the multi-phase core regulator is active and the North Bridge regulator is disabled, as confirmed in the "Typical Application – PVI Mode" schematic (page 5 of FN6880.1). The NB section remains powered but does not regulate; PHASE_NB, UGATE_NB, and related pins are inactive, reducing quiescent current and simplifying layout for uniplane processor designs.
What are the absolute maximum ratings for PVCC supply on the ISL6324ACRZR5381?
The ISL6324ACRZR5381 specifies an absolute maximum PVCC supply voltage of -0.3V to +15V, with recommended operating range of +5V to +12V ±5%. Exceeding +15V risks permanent damage to internal gate drivers; operation below -0.3V violates latch-up immunity. These limits apply separately to PVCC1_2 (core drivers) and PVCC_NB (NB driver) pins.
ISL6324ACRZR5381 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, AMD SVI
- Voltage - Input:
- 5V ~ 12V
- Number of Outputs:
- 2
- Voltage - Output:
- Up to 2V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-QFN (7x7)
ISL6324ACRZR5381 FAQ
1.How can I place an order for ISL6324ACRZR5381 through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6324ACRZR5381 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6324ACRZR5381 reliable?
The price and inventory of ISL6324ACRZR5381 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6324ACRZR5381 is usually 5 days.
3.What payment methods are accepted for ISL6324ACRZR5381?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6324ACRZR5381 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6324ACRZR5381?
ISL6324ACRZR5381 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6324ACRZR5381 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6324ACRZR5381?
For technical support, including ISL6324ACRZR5381 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6324ACRZR5381 requirements.
6.How does Aetrix verify that ISL6324ACRZR5381 is sourced from the original manufacturer or authorized distributors?
All ISL6324ACRZR5381 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6324ACRZR5381 meets industry standards.
7.What is the process for return or replacement of ISL6324ACRZR5381?
All ISL6324ACRZR5381 units undergo pre-shipment inspection (PSI). If there is an issue with ISL6324ACRZR5381, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6324ACRZR5381 part is unused and in its original packaging.
Return procedure for ISL6324ACRZR5381:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ISL6324ACRZR5381 Tags
-
TPS51206DSQR
Texas Instruments
-
TPS51200DRCR
Texas Instruments
-
TPS51200DRCT
Texas Instruments
-
TPS62740DSSR
Texas Instruments
-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi
-
RT9026GSP
Richtek USA Inc.
-
LP2998MRX/NOPB
Texas Instruments
-
TPS51200QDRCRQ1
Texas Instruments
-
DPA423GN-TL
Power Integrations
-
LM10011SD/NOPB
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
