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Renesas ISL6324ACRZ-TR5381
- Part No.:
- ISL6324ACRZ-TR5381
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
ISL6324ACRZ-TR5381.pdf
- Description:
- IC REG CTRLR AMD SVI 2OUT 48QFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,051
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Product details
Overview
ISL6324ACRZ-TR5381 from Renesas (formerly Intersil) is a monolithic dual PWM hybrid controller for AMD SVI/PVI split-plane and uniplane processors, delivering ±0.5% system voltage accuracy over temperature, 2–4-phase core regulation with integrated drivers, and single-phase North Bridge (VDDNB) regulation. It supports I²C programmable voltage offset, droop control, and PSI_L-based phase shedding for high-efficiency CPU power delivery in desktop and server motherboards.
For engineers reviewing the ISL6324ACRZ-TR5381 datasheet, ISL6324ACRZ-TR5381 pinout, ISL6324ACRZ-TR5381 application, or ISL6324ACRZ-TR5381 equivalent, key selection criteria include SVI/PVI mode flexibility, differential DCR current sensing for load-line programming, adaptive phase alignment (APA), dual-edge modulation for fast transient response, and 48-pin 7×7 QFN packaging with integrated gate drivers.
Technical Context
The ISL6324ACRZ-TR5381 implements a hybrid architecture: a multi-phase (2–4-phase) VR controller for VDD core using fully differential continuous DCR sensing and APA, plus a dedicated single-phase VR controller for VDDNB. It decodes AMD's 6-bit parallel VID (PVI) or 2-wire serial VID (SVI) interface based on VID1/SEL latching at enable.
Its control loop integrates dual-edge modulation, programmable droop via RSET, I²C-configurable OVP/PGOOD thresholds, and PSI_L-triggered phase shedding with user-defined cycle count and target phase count. Gate drive bias is configurable from 5V to 12V per PVCC1_2 and PVCC_NB rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Voltage Accuracy | ±0.5% over temperature - enables tight regulation for AMD processor core voltage compliance |
| Switching Frequency Range | 0.08–1 MHz - selectable via FS resistor; supports high-frequency designs to reduce passive size |
| Phase Support | 2–4-phase core + 1-phase NB - matches AMD uniplane and split-plane processor requirements |
| Current Sensing | Fully differential DCR sensing - provides precise channel current balance and load-line programming |
| I²C Interface | AMD-compliant 2-wire SVI + full I²C - enables independent voltage margining, OVP/PGOOD threshold setting, and PSI_L enhancement |
| Package | 48-pin 7×7 mm QFN - RoHS-compliant, thermally enhanced with exposed pad for high-power CPU VR applications |
| Operating Temp | 0°C to +70°C - validated for commercial-grade motherboard power delivery environments |
Pinout & Package
ISL6324ACRZ-TR5381 is housed in a 48-lead 7×7 mm QFN package with exposed thermal pad (PKG DWG L48.7x7). Pin functions are validated per FN6880.1 datasheet Rev. 1.0 (April 29, 2010).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VID1/SEL | Mode selection input | Latches SVI or PVI operation at EN rise; determines function of VID0/VFIXEN, VID2/SVC, VID3/SVD pins |
| VSEN / RGND | Differential remote sense pair | Connects to processor VDDFB[H,L] for precision core voltage feedback; rejects PCB trace IR drop |
| ISEN1+ to ISEN4+, ISEN_NB+ | Current sense positive inputs | Interface with DCR sense networks for per-channel current monitoring and balancing |
| ISEN1− to ISEN4−, ISEN_NB− | Current sense negative inputs | Complete differential current sensing path; enables accurate load-line droop and OCP |
| UGATE1/2/NB, LGATE1/2/NB | Integrated gate drivers | Directly drive external MOSFETs; eliminate need for discrete driver ICs in compact VR designs |
| SCL / SDA | I²C bidirectional interface | Supports AMD SVI protocol and extended I²C commands for voltage offset, OVP, PGOOD, and PSI_L tuning |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive Phase Alignment (APA) | Adjustable trip level via APA pin resistor - dynamically aligns phase timing to minimize output ripple during transients |
| Dual-Edge Modulation | Enables sub-cycle response to high di/dt load steps - reduces voltage undershoot without increasing switching frequency |
| Programmable Droop | Configured via RSET and FS pin connection - allows reduction of bulk output capacitance while maintaining stability |
| PSI_L-Controlled Phase Shedding | I²C-programmable target phase count and transition cycles - optimizes light-load efficiency without compromising wake-up response |
| Integrated Dual Driver Blocks | Separate PVCC1_2 and PVCC_NB supplies - supports independent gate bias optimization for core and NB FETs |
Applications
| Desktop Motherboard VRM | Server CPU Power Delivery |
|---|---|
Use Scenario: High-current core voltage regulation for AMD Phenom II and early FX-series CPUs on ATX motherboards. IC Role / Device Role / Timing Role: Dual-output hybrid controller managing VDD (2–4-phase) and VDDNB (1-phase) with SVI interface handshake and I²C margining. Use Value: Enables ±0.5% core voltage accuracy and fast transient response required for stable overclocking and dynamic frequency scaling. | Use Scenario: Multi-socket server board supplying AMD Opteron processors with split-plane power architecture. IC Role / Device Role / Timing Role: Primary VR controller implementing PVI mode for legacy Opteron VID decoding and simultaneous NB regulation. Use Value: Reduces BOM count by integrating two independent VR controllers and gate drivers in one 7×7 mm QFN. |
| Embedded Computing Platform | Workstation Graphics Power |
Use Scenario: Compact embedded system requiring AMD G-Series APU core and NB power with thermal headroom. IC Role / Device Role / Timing Role: Core VRM controller operating in SVI mode with I²C-configurable PGOOD thresholds and droop for low-noise operation. Use Value: Supports programmable voltage offset and load-line tuning to meet strict EMI and thermal constraints in fanless enclosures. | Use Scenario: High-performance workstation supporting discrete GPU alongside AMD CPU with shared VRM resources. IC Role / Device Role / Timing Role: Dual-output controller powering CPU core and chipset northbridge while coordinating with GPU VRMs via synchronized soft-start. Use Value: Simultaneous digital soft-start of both outputs prevents inrush current conflicts and ensures system-level power sequencing integrity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output CPU voltage regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6323IRZ | 3-phase-only core controller; no integrated NB regulator; lacks I²C interface and APA | Requires external NB controller and separate SVI interface logic; limited margining capability | Choose when only core regulation is needed and cost-per-phase is prioritized over integration |
| RT8802AGQW | Single-chip 4+1 phase controller with integrated NB; supports Intel IMVP-7, not AMD SVI/PVI | Designed for Intel CPUs; incompatible VID protocol and register map; different pinout and compensation scheme | Choose for Intel platform designs requiring identical phase count and footprint compatibility |
Compared with ISL6324ACRZ-TR5381, ISL6323IRZ offers lower integration and no NB support, while RT8802AGQW targets Intel platforms with incompatible control protocols-neither is pin-compatible or functionally interchangeable without redesign.
Availability
ISL6324ACRZ-TR5381 is available at Aetrix Electronics and suitable for desktop motherboard VRMs, server CPU power delivery systems, and embedded computing platforms requiring stable component supply and long-term lifecycle support.
Supply support for ISL6324ACRZ-TR5381 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and maintains its high-performance analog and power management portfolio for computing, industrial, and automotive markets.
The ISL6324ACRZ-TR5381 belongs to Renesas' legacy Intersil CPU voltage regulator controller product line, designed specifically for AMD processor power architectures requiring SVI/PVI interface support and multi-phase core + single-phase NB regulation.
FAQ
What interface protocols does the ISL6324ACRZ-TR5381 support?
The ISL6324ACRZ-TR5381 supports both AMD Serial VID (SVI) and Parallel VID (PVI) interfaces. Mode selection is determined by the state of the VID1/SEL pin at EN assertion. In SVI mode, it uses SDA/SCL for 2-wire communication; in PVI mode, it decodes six VID inputs (VID0–VID5) for DAC voltage setting. The ISL6324ACRZ-TR5381 also features a full I²C interface for extended configuration beyond VID.
How does the ISL6324ACRZ-TR5381 implement phase shedding for efficiency?
The ISL6324ACRZ-TR5381 implements phase shedding via the PSI_L signal, which triggers automatic reduction of active phases in the core VR. The target number of phases and the number of PWM cycles between phase transitions are both programmable through the I²C interface. This allows fine-grained control over light-load efficiency without sacrificing transient response during wake-up events. The ISL6324ACRZ-TR5381 retains full functionality of the remaining active phases during shedding.
What is the role of the RSET pin on the ISL6324ACRZ-TR5381?
The RSET pin on the ISL6324ACRZ-TR5381 sets the effective value of internal current-sense resistors used for DCR-based current monitoring. Connected to VCC via an external resistor (20kΩ–80kΩ), it calibrates sensed current tolerance for load-line programming, channel balancing, and overcurrent protection. A 0.1µF capacitor in parallel improves noise immunity. The ISL6324ACRZ-TR5381 uses this setting across both core and NB current-sense paths.
Does the ISL6324ACRZ-TR5381 support differential remote voltage sensing?
Yes, the ISL6324ACRZ-TR5381 supports precision differential remote voltage sensing via the VSEN and RGND pins. These inputs connect directly to the processor's VDDFB[H,L] sense points, enabling rejection of PCB trace resistance voltage drop and ensuring ±0.5% system accuracy over temperature. This sensing architecture is mandatory for meeting AMD processor core voltage regulation specifications and is used exclusively by the core VR controller-not the NB section.
What are the gate drive voltage ranges supported by the ISL6324ACRZ-TR5381?
The ISL6324ACRZ-TR5381 supports variable gate drive bias from 5V to 12V on both PVCC1_2 (core drivers) and PVCC_NB (North Bridge driver) pins. This allows optimization of MOSFET switching speed and conduction loss for specific FET selections. Upper gate drive source/sink resistance is 2.0Ω/1.65Ω (core) and 2.0Ω/1.65Ω (NB); lower gate drive is 1.25Ω/0.80Ω. The ISL6324ACRZ-TR5381 maintains these drive strengths across its full bias range.
ISL6324ACRZ-TR5381 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Controller, AMD SVI
- Voltage - Input:
- 5V ~ 12V
- Number of Outputs:
- 2
- Voltage - Output:
- Up to 2V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-QFN (7x7)
ISL6324ACRZ-TR5381 FAQ
1.How can I place an order for ISL6324ACRZ-TR5381 through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6324ACRZ-TR5381 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6324ACRZ-TR5381 reliable?
The price and inventory of ISL6324ACRZ-TR5381 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6324ACRZ-TR5381 is usually 5 days.
3.What payment methods are accepted for ISL6324ACRZ-TR5381?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6324ACRZ-TR5381 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6324ACRZ-TR5381?
ISL6324ACRZ-TR5381 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6324ACRZ-TR5381 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6324ACRZ-TR5381?
For technical support, including ISL6324ACRZ-TR5381 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6324ACRZ-TR5381 requirements.
6.How does Aetrix verify that ISL6324ACRZ-TR5381 is sourced from the original manufacturer or authorized distributors?
All ISL6324ACRZ-TR5381 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6324ACRZ-TR5381 meets industry standards.
7.What is the process for return or replacement of ISL6324ACRZ-TR5381?
All ISL6324ACRZ-TR5381 units undergo pre-shipment inspection (PSI). If there is an issue with ISL6324ACRZ-TR5381, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6324ACRZ-TR5381 part is unused and in its original packaging.
Return procedure for ISL6324ACRZ-TR5381:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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