Renesas ISL6333CCRZ
- Part No.:
- ISL6333CCRZ
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
ISL6333CCRZ.pdf
- Description:
- IC REG CTRLR VR11 1OUT 48QFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,715
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Product details
Overview
ISL6333CCRZ from Renesas Electronics (formerly Intersil) is a three-phase buck PWM controller with integrated MOSFET drivers, designed specifically for Intel VR11.1 microprocessor voltage regulation. It delivers ±0.5% system accuracy over temperature, supports 8-bit VID input for DAC-based voltage selection, and features PSI#-enabled phase dropping for light-load efficiency. It operates in 0°C to +70°C ambient and targets high-performance CPU power delivery in desktop and server platforms.
For engineers reviewing the ISL6333CCRZ datasheet, ISL6333CCRZ pinout, ISL6333CCRZ application, or ISL6333CCRZ equivalent, this page provides verified technical context, confirmed pin functions, real-world application mappings, validated alternative options, and supply-chain support details specific to the ISL6333CCRZ variant - not the broader ISL6333 family.
Technical Context
The ISL6333CCRZ implements a fully differential, continuous DCR current sensing architecture across all three phases, enabling precise load-line programming and channel current balancing without external sense resistors. Its Active Pulse Positioning (APP) modulation and Adaptive Phase Alignment (APA) circuits deliver rapid initial response to high di/dt load transients, reducing bulk capacitor count.
This variant integrates dedicated CPURST_N logic for seamless compatibility with Intel Eaglelake chipset platforms and eliminates the IDROOP pin - routing droop current exclusively through the FB pin with droop always enabled. Unlike ISL6333/ISL6333B, it omits Gate Voltage Optimization Technology (GVOT) and Diode Emulation Mode (DEM), aligning with ISL6333A's feature set while adding CPURST_N.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Topology | Three-phase synchronous buck PWM controller with integrated high- and low-side gate drivers |
| Input Voltage Range (PVCC) | +5V to +12V - powers upper/lower MOSFET drivers; enables flexible gate-drive bias selection |
| VID Interface | 8-bit TTL-compatible input - selects output voltage per Intel VR11 DAC table (0.4V–1.6V range) |
| System Accuracy | ±0.5% over temperature (1.0V–1.6V range) - ensures tight core voltage regulation under thermal stress |
| Operating Temperature | 0°C to +70°C - qualified for commercial-grade CPU power applications |
| Switching Frequency | Adjustable up to 1.0 MHz per phase - supports high-frequency operation with smaller magnetics |
| Protection Features | Multi-tiered overvoltage/undervoltage detection, per-channel overcurrent trip, open-sense line prevention |
Pinout & Package
ISL6333CCRZ is housed in a 48-lead, 7 mm × 7 mm QFN package (Pb-free, RoHS-compliant) with exposed thermal pad. Pin assignment matches the ISL6333C variant as documented in FN6520 Rev 3.00, Page 4.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ISEN1+/ISEN1−, ISEN2+/ISEN2−, ISEN3+/ISEN3− | Differential current sense inputs | Enable accurate, offset-compensated DCR sensing per phase for load-line control and current balance |
| UGATE1/2/3, LGATE1/2/3, BOOT1/2/3, PHASE1/2/3 | Integrated gate drive interface | Direct connection to external MOSFETs; includes shoot-through protection and adaptive non-overlap timing |
| PSI#, CPURST_N | Low-power state control inputs | Joint logic enables optimized phase-dropping and reduced quiescent current during light loads (Eaglelake-compatible) |
| VID0–VID7, IMON, VSEN, RGND, FB, COMP | Voltage regulation interface | Supports Intel VR11.1 protocol, remote sensing, current monitoring, and loop compensation |
| VCC, PUVCC, PVCC1, PVCC2, PVCC3, GND | Power supply terminals | Separate bias (5V) and driver rails (5–12V) ensure noise isolation and robust gate driving capability |
Key Features
| Feature | Design Value |
|---|---|
| Intel VR11.1 compliance | Full support for VR11.1 signaling including IMON current reporting, PSI#-driven phase management, and dynamic VID transitions |
| CPURST_N integration | Eliminates external circuitry required for proper PSI# sequencing on Intel Eaglelake platforms - reduces BOM and layout complexity |
| Active Pulse Positioning (APP) | Accelerates transient response onset by dynamically adjusting pulse edges - lowers peak voltage deviation during load steps |
| Adaptive Phase Alignment (APA) | Aligns switching edges across phases based on load conditions - improves current sharing and reduces RMS input ripple |
| Differential remote sensing | Compensates for PCB IR drop between regulator and CPU die - maintains ±0.5% regulation at point-of-load |
| Programmable soft-start ramp | Configurable via external resistor on SS pin - prevents inrush current and enables controlled voltage ramp-up |
Applications
| Desktop CPU Power Delivery | Server Processor VRM |
|---|---|
Use Scenario: Regulating core voltage for dual-socket Intel Xeon processors in 1U rack servers with strict thermal and efficiency requirements. IC Role / Device Role / Timing Role: Primary three-phase PWM controller managing gate drive signals, current sensing, and VR11.1 communication with the CPU. Use Value: Enables phase dropping via PSI#/CPURST_N to reduce idle power by >30%, while maintaining fast transient response during burst workloads. |
Use Scenario: Powering high-end Core i7/i9 desktop CPUs with dynamic voltage scaling and aggressive load-step demands. IC Role / Device Role / Timing Role: Central voltage regulation IC coordinating three synchronous buck stages, remote sensing, and VID decoding. Use Value: APP+APA modulation cuts voltage undershoot during 50A/µs load steps by up to 40mV versus legacy controllers - improving stability margin. |
| Intel Eaglelake Platform Support | VR11.1-Compatible Motherboard VRM |
Use Scenario: Implementing compliant VRM on motherboards using Intel Eaglelake chipsets requiring coordinated reset and low-power state entry. IC Role / Device Role / Timing Role: VR11.1 controller with integrated CPURST_N handling - replaces discrete logic needed for PSI# timing alignment. Use Value: Removes need for external RC networks or CPLD-based PSI# conditioning - simplifies design validation and reduces component count. |
Use Scenario: Designing ATX motherboard VRMs targeting Intel VR11.1 specification compliance for OEM qualification. IC Role / Device Role / Timing Role: Reference-grade PWM controller providing IMON feedback, dynamic VID compensation, and multi-tier OVP/UVP. Use Value: Built-in ±0.5% system accuracy and differential remote sensing meet Intel VR11.1 tolerance requirements without calibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar three-phase VR11.1 controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6333ACRZ | Lacks CPURST_N pin; retains IDROOP pin routed to FB; same droop-always-enabled behavior | Requires external CPURST_N conditioning circuitry for Eaglelake platforms; otherwise functionally identical in VR11.1 operation | Select ISL6333ACRZ only if Eaglelake compatibility is not required and existing designs use IDROOP-to-FB routing. |
| ISL6333CIRZ | Identical feature set and pinout; rated for -40°C to +85°C industrial temperature range | Valid for extended-temperature environments (e.g., industrial PCs, embedded servers) where ISL6333CCRZ's 0°C–70°C range is insufficient | Choose ISL6333CIRZ when operating ambient exceeds +70°C or when long-term reliability at temperature extremes is critical. |
Compared with ISL6333CCRZ, ISL6333ACRZ requires additional board-level logic for Eaglelake CPURST_N handling, while ISL6333CIRZ offers identical functionality with extended thermal qualification - making it the direct upgrade path for harsh-environment deployments.
Availability
ISL6333CCRZ is available at Aetrix Electronics and suitable for desktop motherboard VRMs, server processor power delivery systems, and Intel Eaglelake platform designs requiring stable component supply, consistent parametric performance, and long-term production continuity.
Supply support for ISL6333CCRZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics acquired Intersil in 2017 and maintains full product support, documentation, and manufacturing continuity for the ISL6333 family.
The ISL6333 series was developed to address Intel VR11.1 microprocessor power requirements - emphasizing precision regulation, light-load efficiency, and seamless platform integration for high-performance computing applications.
FAQ
What distinguishes ISL6333CCRZ from other ISL6333 variants?
The ISL6333CCRZ is the commercial-temperature (0°C to +70°C), CPURST_N–enabled variant of the ISL6333C family. Unlike ISL6333/ISL6333B, it excludes Gate Voltage Optimization Technology and Diode Emulation Mode. Compared to ISL6333ACRZ, it adds CPURST_N for direct Eaglelake compatibility and removes the IDROOP pin - routing droop current exclusively through FB with droop always active. This makes ISL6333CCRZ uniquely suited for cost-sensitive, Eaglelake-based desktop platforms requiring VR11.1 compliance.
Does ISL6333CCRZ support coupled inductor operation?
Yes, ISL6333CCRZ supports coupled inductor operation. The FS pin determines mode: tying the RFS resistor to VCC configures the controller for coupled inductor topology, while grounding RFS selects standard inductor mode. This flexibility allows designers to optimize for either reduced output ripple (coupled) or simplified magnetics layout (standard), with no change to ISL6333CCRZ firmware or configuration - only external resistor placement.
How does the PSI# and CPURST_N interaction work on ISL6333CCRZ?
On ISL6333CCRZ, PSI# and CPURST_N jointly control low-power state entry. When both pins are asserted low, the controller drops to single-phase operation and activates light-load optimizations - including reduced gate drive strength and modified current-sense gain. The CPURST_N signal synchronizes this transition with CPU reset timing, eliminating race conditions common in Eaglelake platforms. This dual-input scheme replaces external glue logic previously needed to coordinate PSI# with chipset reset sequences.
What is the role of the APA pin on ISL6333CCRZ?
The APA (Adaptive Phase Alignment) pin on ISL6333CCRZ sets the trip threshold for phase-alignment circuitry. A resistor from APA to COMP establishes the current level at which phase edges are dynamically realigned to improve current sharing. For example, a 100 kΩ resistor yields ~100 µA trip current - triggering alignment when channel current imbalance exceeds that threshold. This feature directly enhances thermal distribution across MOSFETs and reduces input capacitor RMS current by up to 25% in three-phase operation.
Can ISL6333CCRZ be used without remote sensing?
Yes, ISL6333CCRZ can operate in local-sense mode. If VSEN and RGND are tied together at the controller's output, the internal differential amplifier defaults to single-ended sensing - though system accuracy degrades to ±1.0% due to uncorrected PCB voltage drop. Remote sensing is strongly recommended for VR11.1 compliance, as the ±0.5% accuracy spec assumes differential measurement. Local-sense operation remains viable for prototyping or non-critical applications where layout constraints prevent remote trace routing.
ISL6333CCRZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VR11
- Voltage - Input:
- 5V ~ 12V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.5V ~ 1.6V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-QFN (7x7)
ISL6333CCRZ FAQ
1.How can I place an order for ISL6333CCRZ through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6333CCRZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6333CCRZ reliable?
The price and inventory of ISL6333CCRZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6333CCRZ is usually 5 days.
3.What payment methods are accepted for ISL6333CCRZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6333CCRZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6333CCRZ?
ISL6333CCRZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6333CCRZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6333CCRZ?
For technical support, including ISL6333CCRZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6333CCRZ requirements.
6.How does Aetrix verify that ISL6333CCRZ is sourced from the original manufacturer or authorized distributors?
All ISL6333CCRZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6333CCRZ meets industry standards.
7.What is the process for return or replacement of ISL6333CCRZ?
All ISL6333CCRZ units undergo pre-shipment inspection (PSI). If there is an issue with ISL6333CCRZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6333CCRZ part is unused and in its original packaging.
Return procedure for ISL6333CCRZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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