Renesas ISL6336DIRZ-T
- Part No.:
- ISL6336DIRZ-T
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
ISL6336DIRZ-T.pdf
- Description:
- IC REG CTRLR VR11.1 1OUT 48QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL6336DIRZ-T from Renesas (formerly Intersil) is a VR11.1-compliant 6-phase PWM controller with droop disabled, designed for high-efficiency multiphase buck voltage regulation in CPU and memory power delivery. It supports 1–6-phase operation, active phase dropping via PSI#, differential remote sensing, and precision load current monitoring via IMON. Key confirmed specs: ±0.5% closed-loop system accuracy over load/line/temperature, adjustable switching frequency up to 1 MHz per phase, and integrated thermal compensation using NTC thermistor input on TM pin.
For engineers reviewing the ISL6336DIRZ-T datasheet, ISL6336DIRZ-T pinout, ISL6336DIRZ-T application, or ISL6336DIRZ-T equivalent, this page delivers verified technical context, validated pin functions, real-world application mappings for server/memory VRs, and two confirmed alternative controllers with documented functional and interface differences - all grounded in the FN8320 Rev 0.00 datasheet and Renesas product documentation.
Technical Context
The ISL6336DIRZ-T implements proprietary Active Pulse Positioning (APP) and Adaptive Phase Alignment (APA) modulation to minimize phase-to-phase timing skew and improve transient response. Its architecture enables dynamic phase adding/dropping under PSI# control while maintaining channel-current balancing across all active phases using differential current sense inputs (ISENx±) for both DCR and discrete resistor sensing.
It integrates a unity-gain differential remote-sense amplifier (VSEN/RGND → VDIFF), a programmable offset circuit (OFS/REF/DAC), and dual enable inputs (EN_PWR/EN_VTT) with precise threshold detection (0.85 V rising, 0.75 V falling). The IMON pin provides thermally compensated average load current output clamped at 1.11 V, directly usable by host processors for telemetry and OCP.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phases | 6-phase interleaved PWM controller; configurable down to 1-phase via PWMx pin strapping and PSI# logic. |
| VR Compliance | Intel VR11.1 compliant with droop disabled - meets VID decoding, reporting, and sequencing requirements except droop mode. |
| System Accuracy | ±0.5% closed-loop regulation accuracy over -40°C to +85°C for VID = 1.0–1.6 V; critical for stable core voltage under dynamic CPU loads. |
| Switching Frequency | Adjustable 80 kHz to 1 MHz per phase via FS pin resistor; enables optimization of efficiency vs. size in high-density VR designs. |
| Current Sensing | Differential ISEN± inputs support both precision resistor and DCR-based sensing; enables accurate per-phase current limiting and channel balancing. |
| Thermal Compensation | Integrated NTC-based temperature compensation via TM/TCOMP pins; adjusts IMON and OCP thresholds to counteract inductor DCR drift. |
| Remote Sensing | Differential VSEN/RGND input with VDIFF output eliminates ground potential error; improves regulation accuracy at point-of-load. |
Pinout & Package
ISL6336DIRZ-T is housed in a Pb-free, RoHS-compliant 48-lead QFN package (7 mm × 7 mm, JEDEC MO-220 QFN outline L48.7x7) with exposed thermal pad. Pin count and layout match the ISL6336D family specification in FN8320 Rev 0.00.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VID0–VID7 | Voltage ID input | 8-bit digital input for microprocessor VID code; sets target output voltage with Dynamic VID™ support for on-the-fly changes. |
| IMON | Average load current monitor output | Thermally compensated analog voltage proportional to total load current; clamped at 1.11 V for overcurrent shutdown initiation. |
| ISEN1+ / ISEN1− … ISEN6+ / ISEN6− | Differential current sense inputs | Per-phase current measurement for balancing, OCP, and DCR/resistor-based sensing; unused channels left open. |
| PWM1–PWM6 | Phase drive outputs | Open-drain PWM signals driving external gate drivers; phase count configured via strapping (e.g., tie PWM6 to VCC for 5-phase). |
| PSI# | Processor sleep indication input | Active-low signal triggering automatic phase reduction (1- or 2-phase) to maintain high light-load efficiency without firmware intervention. |
| VSEN / RGND / VDIFF | Differential remote sense interface | VSEN and RGND connect to load-side sense points; VDIFF delivers amplified differential error signal to regulation loop. |
| EN_PWR / EN_VTT | Threshold-sensitive enable inputs | Independent 0.85 V rising-threshold enables; coordinate startup with 12 V rail and VTT regulator for sequenced power-up. |
| TM / TCOMP | Thermal monitoring interface | TM accepts NTC voltage divider; TCOMP scales internal thermal compensation gain for IMON and OCP calibration vs. temperature. |
Key Features
| Feature | Design Value |
|---|---|
| Active Phase Adding/Dropping | Enables seamless transition between 1–6 active phases under PSI# control - reduces magnetic core losses and improves light-load efficiency without sacrificing heavy-load transient response. |
| Proprietary APP/APA Modulation | Minimizes phase timing skew and ripple cancellation loss across interleaved channels - achieves faster load-step response with fewer bulk capacitors. |
| Differential Remote Voltage Sensing | Eliminates PCB trace IR drop error between controller and load - ensures ±0.5% regulation accuracy at point-of-load under varying current conditions. |
| Programmable Output Voltage Offset | OFS pin allows DC offset injection independent of VID setting - supports margining, adaptive voltage scaling, and custom VDDQ/VDDIO tracking in memory VR applications. |
| Integrated Thermal Compensation | Uses TM pin NTC voltage to dynamically scale IMON and OCP thresholds - maintains current-sense accuracy across -40°C to +85°C ambient without external compensation circuitry. |
Applications
| Server CPU Core VR | DDR5 Memory VDDQ VR |
|---|---|
Use Scenario: High-current, low-voltage regulation for dual-socket Xeon Scalable processors requiring fast transient response and strict voltage tolerance. IC Role / Device Role / Timing Role: Primary 6-phase PWM controller managing synchronous buck stages; interfaces with CPU via VID/PSI#/IMON for closed-loop telemetry and phase-state coordination. Use Value: APP/APA modulation and 1–6-phase scalability deliver sub-10 µs transient recovery with <±0.5% regulation - meeting Intel VR11.1 spec for core rail stability under 50 A/µs load steps. | Use Scenario: Precision 1.25 V or 1.1 V regulation for DDR5 memory modules with tight voltage margins and thermal derating requirements. IC Role / Device Role / Timing Role: Multiphase controller implementing differential remote sensing and programmable OFS offset to track VDDQ/VDDIO ratios and support memory margining tests. Use Value: Integrated thermal compensation maintains ±1% current-sense accuracy across operating temperature - enabling reliable OCP and load-line calibration for JEDEC-compliant DDR5 power validation. |
| AI Accelerator GPU VR | High-Density FPGA Core VR |
Use Scenario: Power delivery for PCIe-based AI accelerators with bursty, high-peak current demands and aggressive thermal constraints. IC Role / Device Role / Timing Role: 6-phase controller using PSI#-driven phase dropping and IMON telemetry to coordinate with accelerator firmware for dynamic power state transitions. Use Value: Adjustable 80 kHz–1 MHz switching frequency allows optimization for low EMI (sub-150 kHz) or high efficiency (≥500 kHz) - critical for co-packaged GPU+VR thermal management. | Use Scenario: Compact, high-efficiency core rail for large-scale FPGAs where board space and thermal density limit passive component count. IC Role / Device Role / Timing Role: Controller implementing DCR current sensing and coupled inductor compatibility to reduce component count and footprint while maintaining per-phase current balance. Use Value: Differential VSEN/RGND sensing and ±0.5% closed-loop accuracy ensure stable 0.85 V core supply under 30 A load transients - preventing configuration errors during FPGA bitstream loading. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multiphase PWM controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6336CRZ-T | Droop enabled; includes VR11.x droop mode for legacy CPU compatibility; same pinout and 6-phase capability. | Required for Intel VR11.x CPUs needing droop-based load-line programming; not suitable where droop is prohibited (e.g., some memory VRs). | Select ISL6336CRZ-T only when droop compliance is mandatory; ISL6336DIRZ-T is preferred for general-purpose or droop-disabled systems. |
| RT8803AGQW | 6-phase controller with integrated MOSFET drivers; no IMON telemetry; supports VR12.0/IMVP8 but lacks VR11.1-specific PSI# behavior. | Targeted at cost-sensitive client platforms; lacks thermal compensation and differential remote sensing - unsuitable for high-accuracy server/memory VRs. | Choose RT8803AGQW for compact, driver-integrated solutions where telemetry and precision are secondary; ISL6336DIRZ-T remains optimal for telemetry-rich, thermally compensated designs. |
Compared with ISL6336CRZ-T, ISL6336DIRZ-T removes droop functionality for tighter voltage regulation in non-CPU applications, while versus RT8803AGQW it retains superior accuracy, thermal compensation, and IMON telemetry - making it the only choice for DDR5 memory and high-end server VRs demanding VR11.1 compliance without droop.
Availability
ISL6336DIRZ-T is available at Aetrix Electronics and suitable for server CPU core VRs, DDR5 memory VDDQ regulators, AI accelerator GPU power supplies, and high-density FPGA core rails requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-compliant sourcing.
Supply support for ISL6336DIRZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and maintains full support for the ISL6336D family. Renesas is a global semiconductor leader specializing in microcontrollers, analog, power, and connectivity solutions.
The ISL6336DIRZ-T belongs to Renesas' high-performance multiphase PWM controller product line, engineered specifically for precision voltage regulation in datacenter, AI, and high-speed memory subsystems where VR11.1 compliance, thermal accuracy, and telemetry integrity are critical.
FAQ
What is the primary function of the ISL6336DIRZ-T in a power delivery system?
The ISL6336DIRZ-T serves as a 6-phase VR11.1-compliant PWM controller that regulates core/memories voltages using interleaved synchronous buck topology. It drives external gate drivers via PWM1–PWM6 outputs, monitors load current via IMON, and coordinates phase states using PSI# - all while maintaining ±0.5% closed-loop accuracy. Its design centers on high-efficiency, fast-transient CPU and memory power delivery.
Does the ISL6336DIRZ-T support differential remote voltage sensing, and how is it implemented?
Yes, the ISL6336DIRZ-T supports true differential remote sensing via dedicated VSEN and RGND pins feeding into an internal unity-gain amplifier whose output (VDIFF) feeds the error amplifier. This eliminates PCB trace resistance error between controller and load, ensuring regulation accuracy remains within ±0.5% at the point-of-load - a key requirement for modern low-voltage, high-current applications like DDR5 VDDQ.
How does the ISL6336DIRZ-T handle thermal compensation for current sensing?
The ISL6336DIRZ-T uses the TM pin to read voltage from an NTC thermistor network and the TCOMP pin to scale internal thermal compensation gain. This dynamically adjusts both the IMON output voltage and overcurrent protection thresholds to compensate for inductor DCR drift across temperature - eliminating need for external compensation circuits and preserving ±1% current-sense accuracy from -40°C to +85°C.
Can the ISL6336DIRZ-T operate with fewer than six phases, and how is phase count configured?
Yes, the ISL6336DIRZ-T supports 1–6-phase operation. Phase count is set by strapping specific PWMx pins to VCC (e.g., tie PWM6 to VCC for 5-phase) and/or using PSI# assertion to trigger automatic phase dropping. The datasheet confirms single-phase operation is achieved by tying PWM2 to VCC and PSI# to GND - enabling flexible design reuse across different power levels without hardware change.
What is the role of the OFS pin on the ISL6336DIRZ-T, and how is it used in practice?
The OFS pin on the ISL6336DIRZ-T enables programmable DC voltage offset injection independent of VID setting. By connecting an external resistor between OFS and GND (or VCC), designers generate a precision offset current that creates a calibrated voltage difference between DAC and REF pins - supporting memory margining, adaptive voltage scaling, and VDDQ/VDDIO tracking in DDR5 VR designs per JEDEC specifications.
ISL6336DIRZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VR11.1
- Voltage - Input:
- 4.75V ~ 5.25V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.5V ~ 1.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-QFN (7x7)
ISL6336DIRZ-T FAQ
1.How can I place an order for ISL6336DIRZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6336DIRZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6336DIRZ-T reliable?
The price and inventory of ISL6336DIRZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6336DIRZ-T is usually 5 days.
3.What payment methods are accepted for ISL6336DIRZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6336DIRZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6336DIRZ-T?
ISL6336DIRZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6336DIRZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6336DIRZ-T?
For technical support, including ISL6336DIRZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6336DIRZ-T requirements.
6.How does Aetrix verify that ISL6336DIRZ-T is sourced from the original manufacturer or authorized distributors?
All ISL6336DIRZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6336DIRZ-T meets industry standards.
7.What is the process for return or replacement of ISL6336DIRZ-T?
All ISL6336DIRZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL6336DIRZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6336DIRZ-T part is unused and in its original packaging.
Return procedure for ISL6336DIRZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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