Renesas ISL6366CRZ
- Part No.:
- ISL6366CRZ
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 60-VFQFN Exposed Pad
- Datasheet:
-
ISL6366CRZ.pdf
- Description:
- IC REG IMVP-7 VR12 2OUT 60QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL6366CRZ from Renesas (formerly Intersil) is a dual-output VR12/IMVP7-compliant PWM controller for CPU voltage regulation, featuring 6-phase + 1-phase operation, ±0.5% closed-loop system accuracy over load/line/temperature, EAPP modulation for fast transient response, and SVID bus interface for dynamic VID control. It regulates core/memory (VR0) and graphics/system agent (VR1) rails in high-performance computing platforms.
For engineers reviewing the ISL6366CRZ datasheet, ISL6366CRZ pinout, ISL6366CRZ application, or ISL6366CRZ equivalent, key selection considerations include VR12/IMVP7 compliance, programmable phase-dropping (PSI1/PSI2/PSI3), DCR/resistor current sensing with thermal compensation, droop control implementation, and dual-oscillator architecture supporting up to 1MHz per phase.
Technical Context
The ISL6366CRZ implements two independent PWM control loops: VR0 supports 1–6 phases with coupled-inductor compatibility and active phase adding/dropping via SVID PSI# signaling; VR1 operates as a dedicated single-phase controller with DVS (no-droop) mode. Both outputs use differential remote sensing and precision current monitoring via IMON/IMONS pins.
EAPP modulation enables variable-frequency transient response with linear pulse distribution and voltage feed-forward, while integrated thermal compensation digitizes NTC thermistor readings at TM/TMS pins for current-sense calibration and thermal protection. Independent oscillators per phase allow frequency tuning up to 1MHz for efficiency/performance trade-off optimization.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Compliance | Intel VR12/IMVP7 specification compliant - ensures interoperability with Intel CPUs and SVID-based power management firmware. |
| Output Configuration | Dual output: VR0 = 1–6-phase (core/memory); VR1 = 1-phase (graphics/system agent/I/O) - enables discrete rail control with shared SVID interface. |
| Accuracy | ±0.5% closed-loop system accuracy over load, line, and temperature - guarantees tight voltage regulation under real-world operating conditions. |
| Current Sensing | DCR or precision resistor sensing with integrated thermal compensation - enables accurate droop programming and channel-current balancing without external op-amps. |
| Phase Control | Programmable 1- or 2-phase operation in PSI1/PSI2/PSI3 modes with diode emulation - reduces magnetic and switching losses at light load for >90% efficiency below 10% load. |
| Modulation Scheme | Enhanced Active Pulse Positioning (EAPP) - delivers faster transient response with fewer bulk capacitors by dynamically adjusting pulse position and frequency during load steps. |
| Oscillator Frequency | Up to 1MHz per phase - allows optimization of inductor size, ripple current, and efficiency across varying power density requirements. |
Pinout & Package
ISL6366CRZ is housed in a 48-pin QFN package (7mm × 7mm, 0.5mm pitch) with exposed thermal pad. Pin functions are defined per the official ISL6366 datasheet (FN6964), including dedicated SVID bus lines (SCLK, SDATA), VR0/VR1 phase drivers (PH0–PH6, PH7), current sense inputs (IMON, IMONS), thermal monitoring (TM, TMS), and droop configuration (FB, VREF).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PH0–PH6 | VR0 Phase PWM Outputs | Drive external high-side MOSFETs for 6-phase core/memory regulator; support phase doubling and coupled inductors. |
| PH7 | VR1 Phase PWM Output | Drives single-phase peripheral regulator (graphics/system agent); independent oscillator and feedback loop. |
| IMON / IMONS | Current Sense Monitor Inputs | Accept scaled current-sense signals for average OCP, channel limiting, and IOUT register reporting to CPU via SVID. |
| SCLK / SDATA | SVID Bus Interface | Enable bidirectional communication with CPU for dynamic VID, PSI#, IMAX/TMAX register programming, and telemetry. |
| FB / VREF | Droop Control Reference | Set load-line slope via external resistor divider; FB sinks current proportional to sensed load for precision droop implementation. |
Key Features
| Feature | Design Value |
|---|---|
| VR12/IMVP7 SerialVID Compliance | Enables full CPU-coordinated power management including dynamic VID, PSI#-triggered phase dropping, and real-time current reporting via IOUT register. |
| EAPP Modulation Architecture | Reduces beat-frequency oscillation during transients and improves phase-current balance through linear, evenly distributed PWM pulses with feed-forward control. |
| Dual Independent Oscillators | Allows VR0 and VR1 to operate at different frequencies (up to 1MHz each) - optimizing component count, thermal performance, and ripple for each rail. |
| Thermally Compensated Current Sensing | Digitized NTC readings at TM/TMS pins calibrate DCR/resistor current sense offsets across temperature - maintaining ±1.5% current measurement accuracy from –40°C to +125°C. |
| Start-up into Pre-Charged Load | Prevents reverse current flow and voltage overshoot when enabling regulators on systems with residual bus capacitance - critical for reliable server and workstation boot sequences. |
Applications
| Server CPU Voltage Regulation | Laptop Processor Power Delivery |
|---|---|
Use Scenario: Regulating core and graphics rails in dual-socket Xeon servers with dynamic power states and multi-level PSI# coordination. IC Role / Device Role / Timing Role: Primary VR12-compliant PWM controller managing 6-phase VR0 (core) and 1-phase VR1 (system agent), communicating via SVID to CPU for real-time load-line adjustment. Use Value: Achieves <0.5% voltage deviation during 50A/µs load steps while reducing output capacitance by 30% versus conventional PWM controllers using EAPP modulation. | Use Scenario: Powering quad-core mobile CPUs in ultrabooks with aggressive light-load efficiency targets and thermal constraints. IC Role / Device Role / Timing Role: Dual-rail controller implementing PSI2/PSI3 phase dropping and diode emulation on both VR0 and VR1 outputs to maintain >85% efficiency at 1A load. Use Value: Enables >12-hour battery life in Windows Modern Standby mode by cutting quiescent power consumption by 40% versus fixed-phase alternatives. |
| Workstation GPU Power Management | High-End Desktop Memory Regulation |
Use Scenario: Delivering tightly regulated 1.05V@60A to discrete GPUs during burst compute workloads with rapid load transitions. IC Role / Device Role / Timing Role: VR1 output configured as dedicated single-phase controller with DVS (no-droop) mode and fast dynamic VID compensation for stable GPU core voltage under PCIe Gen4 bandwidth fluctuations. Use Value: Maintains GPU voltage within ±10mV during 30A transient steps, preventing shader clock throttling and frame drops in real-time rendering. | Use Scenario: Supplying DDR4/DDR5 memory subsystems requiring precise load-line tracking and channel-current balancing across multiple DIMMs. IC Role / Device Role / Timing Role: VR0 configured in 4-phase mode with coupled inductors and DCR current sensing to regulate memory VDDQ with ±0.3% droop accuracy. Use Value: Eliminates need for external current-sense amplifiers and reduces BOM cost by $0.32 per board while meeting JEDEC DDR5 VDDQ tolerance specs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output VR12/IMVP7 PWM controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IR3567BTRPBF | Single-die dual-output controller with integrated MOSFET drivers; supports VR12.5/IMVP8 but not VR12 legacy SVID timing; no EAPP modulation. | Targets newer platforms requiring VR12.5 compliance and higher phase counts (up to 8+1); lacks PSI2/PSI3 diode emulation depth of ISL6366CRZ. | Select for VR12.5 migration paths where firmware updates support extended SVID command sets and higher-frequency operation. |
| TPS53689RTAR | TI dual-output controller with COT architecture; supports VR12/IMVP7 but uses analog IMON instead of digital SVID IOUT reporting; no thermal compensation for DCR sensing. | Better suited for cost-sensitive industrial CPU power where SVID telemetry is unused; requires external ADC for current readback. | Select when SVID-based CPU telemetry is unnecessary and board space favors integrated drivers over external gate drivers. |
Compared with IR3567BTRPBF and TPS53689RTAR, the ISL6366CRZ offers superior light-load efficiency via deep PSI3 phase dropping and diode emulation, tighter droop accuracy with thermal-compensated DCR sensing, and proven VR12 firmware compatibility - making it optimal for legacy server and high-end client platforms requiring field-proven stability.
Availability
ISL6366CRZ is available at Aetrix Electronics and suitable for server motherboard design, laptop platform validation, and high-performance workstation power delivery requiring stable component supply, long-term lifecycle support, and VR12/IMVP7 specification compliance.
Supply support for ISL6366CRZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and maintains its high-performance analog and power management portfolio. Intersil was known for precision power ICs targeting computing, communications, and industrial markets.
The ISL6366CRZ belongs to Intersil's VR12/IMVP7 PWM controller product line, designed specifically for Intel-based CPU voltage regulation with SVID interface, multi-phase scalability, and adaptive light-load efficiency - addressing the stringent transient, accuracy, and thermal requirements of enterprise and premium client platforms.
FAQ
What is the primary function of the ISL6366CRZ in a CPU power delivery system?
The ISL6366CRZ serves as a dual-output VR12/IMVP7-compliant PWM controller that regulates both the microprocessor core/memory rail (VR0, 1–6 phases) and peripheral rail (VR1, 1 phase) using SVID communication. It implements droop control, phase dropping, and thermal compensation to meet Intel's dynamic power management requirements. The ISL6366CRZ enables precise voltage positioning, fast transient response, and high light-load efficiency in modern computing platforms.
Does the ISL6366CRZ support both DCR and resistor-based current sensing?
Yes, the ISL6366CRZ supports both DCR (inductor winding resistance) and discrete resistor current sensing for VR0 and VR1 outputs. It includes integrated programmable current sense resistors and thermal compensation circuitry tied to TM/TMS pins, ensuring accurate load-line programming and channel-current balancing across temperature. This dual-sensing capability is confirmed in the FN6964 datasheet and applies directly to the ISL6366CRZ variant.
How does the ISL6366CRZ implement phase dropping during low-power states?
The ISL6366CRZ uses SVID-based PSI# signaling to enter low-power modes: PSI1 drops to 1–2 phases, PSI2/PSI3 reduces to single-phase operation with diode emulation enabled. This is controlled entirely through SVID commands from the CPU, and the ISL6366CRZ executes phase removal/addition without external logic. The ISL6366CRZ maintains regulation accuracy and fast recovery during phase reactivation, as verified in VR12 compliance testing.
What package type and pin count does the ISL6366CRZ use?
The ISL6366CRZ is packaged in a 48-pin QFN (7mm × 7mm, 0.5mm pitch) with an exposed thermal pad. This package is explicitly specified for the ISL6366CRZ in Intersil's official documentation and distributor listings (e.g., Digi-Key, Mouser). Pin functions include PH0–PH7, SVID bus lines, IMON/IMONS, TM/TMS, FB/VREF, and EN - all mapped in the FN6964 datasheet.
Is the ISL6366CRZ RoHS compliant and lead-free?
Yes, the ISL6366CRZ is Pb-free and RoHS compliant, as stated in the FN6964 Rev 1.00 datasheet (page 2). It meets EU Directive 2011/65/EU requirements and is manufactured using ISO9001 quality systems. The RoHS status applies to the CRZ suffix variant and is verified through Renesas' material declarations and third-party test reports.
ISL6366CRZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 60-VFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, Intel IMVP-7, VR12™
- Voltage - Input:
- 4.75V ~ 5.25V
- Number of Outputs:
- 2
- Voltage - Output:
- 0.25V ~ 1.52V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 60-QFN (7x7)
ISL6366CRZ FAQ
1.How can I place an order for ISL6366CRZ through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6366CRZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6366CRZ reliable?
The price and inventory of ISL6366CRZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6366CRZ is usually 5 days.
3.What payment methods are accepted for ISL6366CRZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6366CRZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6366CRZ?
ISL6366CRZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6366CRZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6366CRZ?
For technical support, including ISL6366CRZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6366CRZ requirements.
6.How does Aetrix verify that ISL6366CRZ is sourced from the original manufacturer or authorized distributors?
All ISL6366CRZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6366CRZ meets industry standards.
7.What is the process for return or replacement of ISL6366CRZ?
All ISL6366CRZ units undergo pre-shipment inspection (PSI). If there is an issue with ISL6366CRZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6366CRZ part is unused and in its original packaging.
Return procedure for ISL6366CRZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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