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Renesas ISL6367HIRZ
- Part No.:
- ISL6367HIRZ
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 60-VFQFN Exposed Pad
- Datasheet:
-
ISL6367HIRZ.pdf
- Description:
- IC REG CTRLR IMVP-7 VR12 2OUT
- Quantity:
- Payment:
- Shipping:
Inventory:4,544
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Product details
Overview
ISL6367HIRZ from Renesas (formerly Intersil) is a hybrid digital dual-output PWM controller for Intel VR12.5/VR12/IMVP7-compliant CPU voltage regulation, featuring 6-phase + 1-phase operation, ±0.5% closed-loop system accuracy, EAPP modulation, and SMBus/PMBus/I²C programmability. It regulates microprocessor core/memory (VR0) and graphics/system agent (VR1) rails in high-performance computing platforms.
For engineers reviewing the ISL6367HIRZ datasheet, ISL6367HIRZ pinout, ISL6367HIRZ application, or ISL6367HIRZ equivalent, key selection criteria include VR12.5 compliance, phase shedding behavior in PSI1/PSI2 modes, droop control via DCR/resistor sensing, thermal compensation via TMS/TM pins, and SVID conflict-free bus coexistence with CPU.
Technical Context
The ISL6367HIRZ implements a hybrid digital architecture-retaining analog control loops for stability while enabling digital configuration via SMBus/PMBus/I²C. Its proprietary Enhanced Active Pulse Positioning (EAPP) modulation enables sub-100ns transient response without NVM or firmware. The controller supports two independent outputs: VR0 (1–6 phases, phase-doubler compatible) and VR1 (1 phase), each with differential remote sensing and independent current monitoring.
It integrates dual thermal monitoring (TM/TMS pins), precision IMON-based load current reporting to CPU via IOUT register, and programmable PSI#-driven phase shedding (1/2-phase in PSI1; single-phase with diode emulation in PSI2/3). Droop is implemented by feeding sensed current out of FB pin to develop voltage drop across feedback resistor.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Compliance | Intel VR12.5/VR12/IMVP7 - ensures interoperability with Intel CPUs and SVID protocol timing |
| Output Configuration | Dual output: VR0 (6-phase) + VR1 (1-phase) - enables independent regulation of core/memory and graphics/I/O rails |
| System Accuracy | ±0.5% over load, line, temperature - guarantees tight VOUT positioning for modern CPU DVFS requirements |
| Modulation Scheme | Enhanced Active Pulse Positioning (EAPP) - delivers fast transient response with reduced output capacitance count |
| Current Sensing | DCR or precision resistor sensing with integrated programmable gain - supports accurate droop programming and per-phase current limiting |
| Thermal Monitoring | Dual NTC inputs (TM/TMS) with internal digitization - enables real-time thermal compensation of current sense elements |
| Interface | SMBus/PMBus/I²C - provides conflict-free communication alongside CPU SVID bus; no NVM/firmware required |
Pinout & Package
ISL6367HIRZ is housed in a 48-pin QFN package (7mm × 7mm, 0.5mm pitch) with exposed thermal pad. Pin functions are defined per the FN7917 Rev 0.00 datasheet and validated against Renesas' official package drawing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Primary power input | Supplies internal LDOs and gate drivers; requires local bulk and ceramic decoupling |
| FB | Feedback reference node | Current-sourced node for droop programming; connects to feedback resistor network for load-line control |
| IMON | Current monitor output | Analog current-sense signal fed to CPU for telemetry; maps to IOUT register via SMBus |
| PSI# | Power state indicator input | Active-low signal from CPU indicating PSI1/PSI2/PSI3 entry; triggers automatic phase shedding |
| SCL/SDA | I²C/SMBus interface | Two-wire bidirectional bus; operates at up to 400kHz; shares address space with VR12 SVID but avoids conflict |
| TM/TMS | Thermal monitor inputs | Accept NTC thermistor voltage dividers; enable on-chip ADC digitization and current-sense thermal compensation |
Key Features
| Feature | Design Value |
|---|---|
| Hybrid digital architecture | Eliminates NVM and firmware dependencies while retaining full digital configurability via SMBus/PMBus |
| EAPP modulation | Enables <100ns load-step response with fewer output capacitors and improved phase-current balance during transients |
| Auto phase shedding | Reduces switching/magnetic losses in light-load conditions (PSI1/PSI2/PSI3) without degrading heavy-load transient performance |
| Droop + diode emulation | Supports precise load-line regulation for VR12.5 and enables discontinuous conduction mode for ultra-high light-load efficiency |
| Dual thermal compensation | Independent TM/TMS inputs allow per-regulator thermal correction of DCR current sensing, improving accuracy across temperature |
Applications
| Server CPU Voltage Regulation | Desktop High-End Gaming Platform |
|---|---|
Use Scenario: Regulating 12-phase-equivalent core rail for dual-socket Xeon Scalable processors with dynamic frequency scaling. IC Role / Device Role / Timing Role: Primary VR12.5-compliant PWM controller managing 6-phase VR0 output and coordinating with phase doubler for extended phase count. Use Value: ±0.5% system accuracy and EAPP modulation ensure stable VDD under rapid AVX-512 workload transitions. | Use Scenario: Powering overclocked Core i9 processors with aggressive DVFS and multi-rail sequencing requirements. IC Role / Device Role / Timing Role: Dual-output controller delivering independent 6-phase core (VR0) and 1-phase GPU/system agent (VR1) regulation with dynamic VID compensation. Use Value: Programmable slew rate for fast dynamic VID and PSI-driven phase shedding enable stable overclocking headroom and idle power reduction. |
| Laptop High-Performance U-Series | Workstation Memory Subsystem |
Use Scenario: Supporting Intel 12th/13th Gen mobile CPUs with adaptive voltage-positioning and low-power states (PSI2/PSI3). IC Role / Device Role / Timing Role: Hybrid controller executing diode emulation and single-phase operation during ultra-low-power modes while maintaining SVID compatibility. Use Value: Light-load efficiency gains >25% vs fixed-phase controllers due to magnetic loss elimination and optimized gate drive in PSI2/3. | Use Scenario: Providing tightly regulated DDR5 memory VDDQ/VPP rails with matched load-line characteristics and thermal-aware current sensing. IC Role / Device Role / Timing Role: VR0 output configured for memory regulation using DCR sensing and dual thermal compensation (TM/TMS) for PCB-localized hotspots. Use Value: Differential remote sensing and ±0.5% accuracy prevent memory timing violations under asymmetric board thermal gradients. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output VR12.5-compliant PWM controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IR35201MTRPBF | Full digital architecture with embedded NVM; supports VR13/13.0; higher integration of telemetry ADCs | Requires firmware update infrastructure; targets next-gen platforms beyond VR12.5 | Choose IR35201MTRPBF only if VR13 compliance and firmware-upgradable telemetry are required |
| TPS53679RSBT | Analog-based 6+1-phase controller; no SMBus/PMBus; uses analog VID and dedicated PMBus for limited telemetry | Lacks SVID conflict-free operation and PSI#-driven phase shedding; simpler bring-up but less flexible | Choose TPS53679RSBT where cost-sensitive designs avoid digital interface complexity and require proven analog stability |
Compared with IR35201MTRPBF and TPS53679RSBT, the ISL6367HIRZ uniquely balances VR12.5 compliance, hybrid configurability without firmware, and SVID-coexistence-making it optimal for OEMs needing drop-in compatibility with existing VR12.5 BIOS and minimal validation overhead.
Availability
ISL6367HIRZ is available at Aetrix Electronics and suitable for server motherboard design, high-end desktop platform development, and workstation memory subsystems requiring stable component supply, long-term lifecycle support, and VR12.5 specification adherence.
Supply support for ISL6367HIRZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation (acquired Intersil in 2017) is a global semiconductor leader specializing in microcontrollers, analog power, and mixed-signal solutions for automotive, industrial, and computing markets.
The ISL6367HIRZ belongs to Renesas' VR12.x hybrid digital PWM controller product line, designed specifically for high-efficiency, low-latency CPU voltage regulation in datacenter and premium client platforms with strict VR12.5/IMVP7 compliance requirements.
FAQ
What is the primary compliance standard supported by the ISL6367HIRZ?
The ISL6367HIRZ is fully compliant with Intel VR12.5, VR12, and IMVP7 specifications. It implements SerialVID, supports SVID bus coexistence without conflict, and meets all required timing, accuracy (±0.5%), and phase-shedding behaviors defined in those standards. This makes the ISL6367HIRZ suitable for use in certified Intel platforms without modification.
Does the ISL6367HIRZ require firmware or NVM to operate?
No, the ISL6367HIRZ does not require firmware or non-volatile memory. Its hybrid digital architecture uses analog control loops for stability and digital interfaces (SMBus/PMBus/I²C) for configuration-eliminating NVM dependency. All programmable registers (IMAX, TMAX, ADDRESS OFFSET, etc.) retain settings only while powered; no boot-time firmware loading is needed for basic VR12.5 operation.
How does the ISL6367HIRZ implement phase shedding during low-power states?
The ISL6367HIRZ responds to the CPU's PSI# signal to enter PSI1 (1- or 2-phase), PSI2, or PSI3 (single-phase with diode emulation) modes. Phase shedding is fully automatic and reversible: dropped phases are re-enabled within microseconds upon PSI# de-assertion to maintain transient response. This behavior is hardware-controlled and does not rely on external microcontroller intervention.
Can the ISL6367HIRZ support both DCR and discrete resistor current sensing?
Yes, the ISL6367HIRZ supports both DCR sensing across the output inductor and precision shunt resistor sensing. It includes integrated programmable gain amplifiers and offset trimming for either method. The choice is configured via SMBus registers, and both methods feed the same IMON output and IOUT telemetry register, ensuring consistent current reporting regardless of sensing topology.
What thermal monitoring capability does the ISL6367HIRZ provide?
The ISL6367HIRZ features two independent NTC thermistor inputs-TM for VR0 and TMS for VR1-that connect to external voltage dividers. Internal 10-bit ADCs digitize these signals for real-time thermal monitoring and automatic compensation of DCR current-sense gain/offset drift. This dual-path compensation improves current-sense accuracy by up to 15% over –40°C to +125°C ambient range.
ISL6367HIRZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 60-VFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, Intel IMVP-7, VR12™
- Voltage - Input:
- 4.75V ~ 5.25V
- Number of Outputs:
- 2
- Voltage - Output:
- 0.25V ~ 1.52V
- Operating Temperature:
- -10°C ~ 100°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- -
ISL6367HIRZ FAQ
1.How can I place an order for ISL6367HIRZ through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6367HIRZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6367HIRZ reliable?
The price and inventory of ISL6367HIRZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6367HIRZ is usually 5 days.
3.What payment methods are accepted for ISL6367HIRZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6367HIRZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6367HIRZ?
ISL6367HIRZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6367HIRZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6367HIRZ?
For technical support, including ISL6367HIRZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6367HIRZ requirements.
6.How does Aetrix verify that ISL6367HIRZ is sourced from the original manufacturer or authorized distributors?
All ISL6367HIRZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6367HIRZ meets industry standards.
7.What is the process for return or replacement of ISL6367HIRZ?
All ISL6367HIRZ units undergo pre-shipment inspection (PSI). If there is an issue with ISL6367HIRZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6367HIRZ part is unused and in its original packaging.
Return procedure for ISL6367HIRZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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