My Inquiry
My Account
Renesas ISL6373IRTZ-T
- Part No.:
- ISL6373IRTZ-T
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
ISL6373IRTZ-T.pdf
- Description:
- IC REG CTRLR INTEL 1OUT 40TQFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,624
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ISL6373IRTZ-T from Intersil is a hybrid digital 4-phase PWM controller compliant with Intel VR12.5/VR12 specifications, designed to regulate microprocessor core or memory voltage rails. It delivers ±0.5% closed-loop system accuracy, supports up to 2MHz per phase switching, implements EAPP modulation for fast transient response, and enables auto-phase shedding across 1–4 phases for light-load efficiency in server and desktop CPU power delivery.
For engineers reviewing the ISL6373IRTZ-T datasheet, ISL6373IRTZ-T pinout, ISL6373IRTZ-T application, or ISL6373IRTZ-T equivalent, key selection criteria include VR12.5/VR12 compliance, SVID/SMBus/PMBus programmability, droop control via FB/IMON, thermal monitoring via TM pin, and phase-shedding behavior in PSI1/PSI2 modes.
Technical Context
The ISL6373IRTZ-T integrates Intersil's patented Enhanced Active Pulse Positioning (EAPP) modulation to achieve sub-100ns load-step response while maintaining linear control and evenly distributed PWM pulses. It supports SerialVID with programmable IMAX, TMAX, BOOT, and ADDRESS OFFSET registers for full VR12.5 core and VR12/VR12.5 memory regulation.
It performs precision current sensing via dedicated resistor or DCR, feeds current data to the FB pin for droop programming, and reports IOUT via SMBus/PMBus. The TM pin digitizes NTC thermistor voltage for thermal compensation of current sense elements and integrated thermal monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Count | Configurable 1–4-phase operation with phase doubler support for scalable high-current output |
| Output Accuracy | ±0.5% over load, line, and temperature - ensures tight VOUT regulation for CPU core/memory rails |
| Switching Frequency | Up to 2MHz per phase - enables compact magnetics and high-density power designs |
| Interface Protocol | SMBus/PMBus/I²C with SVID conflict-free operation - allows coexistence with CPU SVID bus without arbitration |
| Current Sensing | Differential resistor or DCR-based sensing with integrated programmable current sense resistors - enables accurate droop, channel balancing, and OCP |
| Thermal Monitoring | TM pin accepts NTC thermistor input with internal digitization - provides real-time die temperature feedback and current-sense compensation |
| Protection Features | True Catastrophic Failure Protection (CFP), average OCP, per-phase current limiting, open-sense protection - safeguards against hard faults and overload conditions |
Pinout & Package
ISL6373IRTZ-T is housed in a 40-pin QFN package (6mm × 6mm, 0.5mm pitch) with exposed thermal pad. Pin functions are defined per the ISL6373 datasheet Rev 0.00 (May 2013), with dedicated pins for phase control, current sensing, thermal monitoring, and digital interface.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Input supply rail | Power input for controller logic and gate drivers; requires local decoupling near pin |
| VOUT | Output voltage sense | Remote-sensed output voltage feedback point; differential sensing eliminates ground offset errors |
| FB | Droop control node | Current-derived voltage sink for precision load-line programming; connects to feedback resistor network |
| IMON | Current monitor output | Analog current-sense signal used for telemetry reporting (IOUT register) and overcurrent detection |
| TM | Thermal monitor input | Accepts NTC thermistor voltage; internally digitized for thermal compensation and monitoring |
| SCL/SCL1 | I²C/SMBus clock | Two independent clock inputs enable SVID conflict-free dual-bus operation |
| SDA/SDA1 | I²C/SMBus data | Separate data lines for SVID and PMBus/SMBus interfaces to avoid bus contention |
| PSI# | Power state indicator | Active-low input signaling CPU low-power mode; triggers automatic phase shedding (PSI1/PSI2) |
Key Features
| Feature | Design Value |
|---|---|
| EAPP Modulation | Proprietary pulse positioning scheme enabling <100ns transient response without requiring external compensation components |
| Auto Phase Shedding | Dynamic reduction to 1–2 phases in PSI1 and single-phase + diode emulation in PSI2/PSI3 - cuts magnetic and switching losses at light load |
| Droop Control Architecture | FB pin sinks current proportional to sensed load; enables precise, resistor-programmable load-line slope for VR12.5 compliance |
| SVID Conflict-Free Dual Bus | Dedicated SCL1/SDA1 pins allow simultaneous SVID communication with CPU and PMBus/SMBus telemetry with host controller |
| Start-up into Pre-charged Load | Enables safe initialization when output capacitor is already charged - prevents reverse current and inrush stress |
Applications
| Server CPU Core Regulation | Desktop CPU Memory Rail |
|---|---|
Use Scenario: Regulating 1.0V–1.8V core voltage for multi-core Xeon or Core i9 processors under dynamic workloads. IC Role / Device Role / Timing Role: Primary 4-phase VR12.5-compliant PWM controller managing VID updates, phase shedding, and droop via SVID. Use Value: ±0.5% accuracy and EAPP modulation ensure stable core voltage during rapid P-state transitions and AVX-heavy loads. | Use Scenario: Delivering tightly regulated DDR4/DDR5 memory VDDQ or VPP rails in high-end desktop motherboards. IC Role / Device Role / Timing Role: VR12/VR12.5 memory controller supporting SerialVID, dynamic VID compensation, and remote sensing. Use Value: Differential remote sensing and DCR current sensing eliminate PCB layout-induced regulation error for memory subsystem stability. |
| Laptop High-Performance Mode | Workstation GPU Power Management |
Use Scenario: Enabling adaptive power delivery in thin-and-light laptops during Turbo Boost or sustained all-core loads. IC Role / Device Role / Timing Role: Hybrid digital controller executing auto-phase add/drop based on PSI# signals and real-time IMON telemetry. Use Value: Diode emulation in PSI2 mode reduces quiescent current by >40%, extending battery life without sacrificing wake-up responsiveness. | Use Scenario: Managing GPU core voltage in professional workstation graphics cards with aggressive thermal constraints. IC Role / Device Role / Timing Role: Thermal-aware PWM controller using TM pin feedback to compensate current sense drift and adjust OCP thresholds. Use Value: Integrated NTC digitization and thermal compensation maintain ±0.5% regulation accuracy across -40°C to +125°C junction range. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 4-phase VR12.5/VR12 PWM controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IR35201MTRPBF | Full digital architecture with embedded NVM; supports VR12.5 but lacks EAPP modulation and SVID conflict-free dual-bus design | Requires firmware update capability and separate SVID arbitration logic; higher BOM cost due to NVM dependency | Preferred where full digital telemetry logging and programmable loop compensation are required |
| TPS53679RSLR | Analog-based multiphase controller with COT topology; no SMBus/PMBus interface; supports VR12 but not VR12.5 SerialVID | Relies on analog feedback only; no PSI#-driven phase shedding or IMON telemetry reporting | Selected for cost-sensitive, non-SVID systems needing fast transient response without digital interface overhead |
Compared with IR35201MTRPBF and TPS53679RSLR, the ISL6373IRTZ-T uniquely combines VR12.5 compliance, SVID conflict-free dual-bus operation, EAPP modulation, and NVM-free hybrid digital control-enabling simpler design, lower inventory cost, and guaranteed light-load efficiency via hardware-managed phase shedding.
Availability
ISL6373IRTZ-T is available at Aetrix Electronics and suitable for server CPU core regulation, desktop memory rail design, and high-performance laptop power delivery requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for ISL6373IRTZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) designs high-performance analog and mixed-signal ICs for power management, precision analog, and interface applications.
The ISL6373IRTZ-T belongs to Intersil's EAPP Hybrid Digital PWM Controller product line, engineered specifically for Intel VR12.5/VR12-compliant CPU and memory voltage regulation with emphasis on transient performance, light-load efficiency, and SVID interoperability.
FAQ
What is the primary compliance standard supported by the ISL6373IRTZ-T?
The ISL6373IRTZ-T is fully compliant with Intel VR12.5 and VR12 specifications, including SerialVID protocol, programmable IMAX/TMAX registers, and PSI#-driven phase shedding modes. It supports both VR12.5 core and VR12/VR12.5 memory voltage regulation, verified per FN8350 Rev 0.00 datasheet. This compliance ensures seamless integration with Intel 3rd–5th generation Core and Xeon processors requiring strict droop and timing behavior.
Does the ISL6373IRTZ-T require external NVM or firmware for configuration?
No, the ISL6373IRTZ-T uses a hybrid digital architecture that eliminates the need for external NVM or firmware. All configuration-including VID mapping, phase shedding thresholds, and droop slope-is performed via SMBus/PMBus or SVID commands in real time. This NVM-free design reduces BOM cost, simplifies qualification, and avoids firmware versioning issues common in full-digital controllers like the IR35201MTRPBF.
How does the ISL6373IRTZ-T implement droop control without an external DAC or op-amp?
The ISL6373IRTZ-T implements droop control by sinking current from the FB pin proportional to sensed load current (via IMON or DCR). This current develops a precision voltage drop across the external feedback resistor, directly establishing the load-line slope. No external DAC or op-amp is needed because the controller's internal current-source architecture and FB pin sink capability provide fully integrated, resistor-programmable droop per VR12.5 requirements.
Can the ISL6373IRTZ-T operate with only one phase enabled?
Yes, the ISL6373IRTZ-T supports 1-phase operation in ultra-low-power modes (PSI2 and PSI3), including diode emulation for enhanced light-load efficiency. Phase count is dynamically managed: 4-phase at full load, 1–2-phase in PSI1, and single-phase with diode emulation in PSI2/PSI3. This behavior is hardware-controlled and requires no host intervention beyond asserting the PSI# signal.
What thermal monitoring capability does the ISL6373IRTZ-T provide?
The ISL6373IRTZ-T features a dedicated TM pin that accepts voltage from an external NTC thermistor. Internally, this analog voltage is digitized and used for two purposes: real-time thermal monitoring reported via SMBus, and automatic compensation of current-sense element drift across temperature. This integrated thermal path ensures ±0.5% system accuracy is maintained from -40°C to +125°C without external ADC or compensation circuitry.
ISL6373IRTZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VR12, VR12.5
- Voltage - Input:
- 4.75V ~ 5.25V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.25V ~ 3.04V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-TQFN (5x5)
ISL6373IRTZ-T FAQ
1.How can I place an order for ISL6373IRTZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6373IRTZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6373IRTZ-T reliable?
The price and inventory of ISL6373IRTZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6373IRTZ-T is usually 5 days.
3.What payment methods are accepted for ISL6373IRTZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6373IRTZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6373IRTZ-T?
ISL6373IRTZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6373IRTZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6373IRTZ-T?
For technical support, including ISL6373IRTZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6373IRTZ-T requirements.
6.How does Aetrix verify that ISL6373IRTZ-T is sourced from the original manufacturer or authorized distributors?
All ISL6373IRTZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6373IRTZ-T meets industry standards.
7.What is the process for return or replacement of ISL6373IRTZ-T?
All ISL6373IRTZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL6373IRTZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6373IRTZ-T part is unused and in its original packaging.
Return procedure for ISL6373IRTZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ISL6373IRTZ-T Tags
-
TPS51206DSQR
Texas Instruments
-
TPS51200DRCR
Texas Instruments
-
TPS51200DRCT
Texas Instruments
-
TPS62740DSSR
Texas Instruments
-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi
-
RT9026GSP
Richtek USA Inc.
-
LP2998MRX/NOPB
Texas Instruments
-
TPS51200QDRCRQ1
Texas Instruments
-
DPA423GN-TL
Power Integrations
-
LM10011SD/NOPB
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
