Renesas ISL6388HRTZ
- Part No.:
- ISL6388HRTZ
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
ISL6388HRTZ.pdf
- Description:
- IC REG CTRLR INTEL 1OUT 40TQFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,601
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Product details
Overview
ISL6388HRTZ from Renesas (formerly Intersil) is a 6-phase digital PWM controller compliant with Intel VR12.5/VR12 specifications, designed to regulate microprocessor core or memory voltage rails. It delivers programmable droop control (1% precision), supports up to 2MHz per phase, implements auto-phase shedding, and features Advanced Linear EAPP digital control for linear transient response in server and high-end desktop power delivery.
For engineers reviewing the ISL6388HRTZ datasheet, ISL6388HRTZ pinout, ISL6388HRTZ application, or ISL6388HRTZ equivalent, key selection criteria include VR12.5 compliance, SMBus/PMBus/I²C programmability with NVM storage for 8 configurations, PSI#-driven 1–2-phase low-power operation, differential remote sensing (±0.5% accuracy), and DCR/resistor-based current sensing with thermal compensation.
Technical Context
The ISL6388HRTZ implements a patented Advanced Linear EAPP digital control architecture-distinct from conventional non-linear discrete digital controllers-enabling evenly distributed PWM pulses, voltage feed-forward, ramp adjustment, and variable frequency during transients to suppress beat-frequency oscillation. It supports SVID conflict-free bus operation up to 1.5MHz and integrates NVM for storing eight independent configurations including droop, OCP thresholds, and switching frequency.
Current sensing uses either a precision external resistor or inductor DCR, feeding into a digitally programmable 1% droop network for accurate load-line control. The TM pin digitizes NTC thermistor voltage for real-time thermal monitoring and automatic current-sense element compensation, while true input current sensing enables catastrophic failure protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Count | Configurable 1–6 phases; enables dynamic phase shedding for light-load efficiency optimization |
| Max Switching Frequency | 2MHz per phase; supports high-density, low-inductance VR designs with fast transient response |
| Bus Interface | SMBus/PMBus/I²C up to 1.5MHz; SVID-conflict-free for coexistence with CPU bus |
| Droop Accuracy | Programmable 1% precision droop resistor; ensures tight load-line regulation across temperature |
| Remote Sensing Accuracy | ±0.5% differential sensing; eliminates ground potential error between remote/local sense points |
| NVM Capacity | Stores up to 8 full configurations (frequency, OCP, UVP, CFP, droop); enables multi-profile system tuning |
| Thermal Monitoring | Digitized NTC input on TM pin; provides real-time die temperature data and integrated current-sense compensation |
Pinout & Package
ISL6388HRTZ is housed in a Pb-Free (RoHS-compliant), 40-lead, 5mm × 5mm QFN package with exposed thermal pad (Renesas package code HRTZ). Pin functions are defined per the official ISL6388 datasheet Rev 0.00.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Primary power input | Supplies internal LDOs and bias circuitry; rated for 5V to 12V input range |
| VOUT_SENSE+ | Remote voltage sense positive | Differential input for high-accuracy output regulation; rejects common-mode noise |
| VOUT_SENSE− | Remote voltage sense negative | Completes differential pair; enables ±0.5% remote sensing accuracy |
| IMON | Current monitor output | Analog current telemetry signal fed to CPU; used by processor for IOUT register reporting |
| PSI# | Power state indicator input | Active-low signal from CPU indicating PSI1/PSI2/PSI3 low-power mode; triggers phase shedding |
| TM | Thermistor monitor input | Analog input for NTC thermistor; digitized internally for thermal compensation and monitoring |
| SCL/SDA | I²C/SMBus interface | Two-wire bidirectional bus interface supporting PMBus commands and NVM programming |
| EN | Enable input | Threshold-sensitive logic input; coordinates startup timing with other system rails |
Key Features
| Feature | Design Value |
|---|---|
| Advanced Linear EAPP Control | Patented digital architecture delivering linear transient response without beat-frequency oscillation; replaces non-linear discrete control |
| Auto Phase Shedding | Dynamically reduces active phases from 6 to 1 based on load and PSI# status-reducing core and switching losses at light load |
| Differential Remote Sensing | Eliminates ground offset errors between VR and CPU; maintains ±0.5% regulation accuracy under PCB layout variation |
| Programmable NVM Storage | Eight independent configuration banks store droop, OCP, frequency, and fault settings-enabling field-updatable power profiles |
| DCR or Resistor Current Sensing | Supports both methods with calibration; enables accurate channel-current balancing and average overcurrent protection |
Applications
| Server Core Voltage Regulation | High-End Desktop Overclocking Rail |
|---|---|
Use Scenario: Regulating core voltage for dual-socket Xeon Scalable processors in 1U/2U rack servers requiring strict VR12.5 compliance and telemetry. IC Role / Device Role / Timing Role: Primary 6-phase PWM controller managing VID updates, phase shedding, and real-time current reporting via IMON/IOUT. Use Value: Auto-phase shedding and linear EAPP control maintain >90% efficiency at 10% load while delivering sub-10µs transient recovery. | Use Scenario: Powering overclocked Intel Core i9 processors in enthusiast desktop platforms with dynamic VID and aggressive load-line tuning. IC Role / Device Role / Timing Role: Digital VR controller implementing fast dynamic VID compensation (DVC), programmable slew rate, and NVM-stored overclock profiles. Use Value: Eight NVM configurations allow BIOS-switchable power profiles; DCR sensing + thermal compensation ensure stable voltage under sustained AVX workloads. |
| GPU Memory VRM | High-Performance DDR5 Memory Rail |
Use Scenario: Delivering tightly regulated voltage to GDDR6X memory stacks on AI accelerator cards with high peak current demands. IC Role / Device Role / Timing Role: 6-phase controller with differential remote sensing and true input current sensing for catastrophic failure protection. Use Value: ±0.5% remote sensing accuracy prevents memory timing violations; high-common-mode current sense input (VCC−1.5V) supports high-side sensing topologies. | Use Scenario: Supplying DDR5 DIMMs in workstation-class motherboards where JEDEC SPD and Intel XMP require precise VDDQ/VPP regulation. IC Role / Device Role / Timing Role: VR12.5-compliant controller managing memory rail startup into pre-charged load and supporting PSI#-driven low-power states. Use Value: Start-up into pre-charged load avoids inrush damage; PSI2/PSI3 single-phase operation reduces idle power by >40% versus fixed 6-phase mode. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-phase digital PWM controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IR35201MTRPBF | 6-phase controller with integrated MOSFET drivers; lacks NVM storage and SVID conflict-free bus design | Targeted at cost-sensitive server boards without need for CPU telemetry or multi-profile storage | Choose IR35201MTRPBF when driver integration reduces BOM count and NVM is unnecessary |
| TPS53689RTAT | 6-phase controller with CSD (Controlled Slew Rate) architecture; supports only PMBus (no SVID compatibility) | Used in TI-ecosystem industrial and telecom systems where SVID bus sharing is not required | Choose TPS53689RTAT when PMBus-only interface suffices and TI reference designs accelerate time-to-market |
Compared with IR35201MTRPBF and TPS53689RTAT, the ISL6388HRTZ uniquely combines SVID-conflict-free bus operation, 8-bank NVM programmability, and Advanced Linear EAPP control-making it the only option for Intel VR12.5 platforms requiring simultaneous CPU telemetry, multi-profile tuning, and beat-oscillation-free transient response.
Availability
ISL6388HRTZ is available at Aetrix Electronics and suitable for high-performance server core regulation, GPU memory VRM, and DDR5 memory rail applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for ISL6388HRTZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation (formerly Intersil) is a global semiconductor leader specializing in microcontrollers, analog power, and connectivity solutions, operating under ISO9001 quality systems.
The ISL6388HRTZ belongs to Renesas' advanced digital power management portfolio, engineered specifically for Intel VR12/VR12.5-compliant CPU and memory voltage regulation in datacenter, AI acceleration, and high-end client platforms.
FAQ
What is the primary compliance standard supported by the ISL6388HRTZ?
The ISL6388HRTZ is fully compliant with Intel VR12.5 and VR12 specifications for microprocessor core and memory voltage regulation. It supports programmable IMAX, TMAX, BOOT, DVID rate, and address settings required by these standards. Its SVID-conflict-free bus interface ensures seamless coexistence with CPU SVID communication, and its auto-phase shedding and PSI# response meet VR12.5 low-power mode requirements. This compliance is verified in the FN8571 datasheet Rev 0.00.
Does the ISL6388HRTZ support both resistor-based and DCR-based current sensing?
Yes, the ISL6388HRTZ supports both precision external current-sense resistors and inductor DCR sensing. It includes dedicated circuits for calibration, channel-current balancing, average overcurrent protection, and individual phase limiting. The current-sense inputs feature high common-mode range (up to VCC−1.5V) and open-sensing fault detection. These capabilities are documented in the ISL6388HRTZ datasheet sections on current sensing and protection.
How many NVM configuration banks does the ISL6388HRTZ provide, and what parameters can be stored?
The ISL6388HRTZ provides eight independent NVM configuration banks. Each bank stores programmable parameters including switching frequency, droop coefficient, overcurrent protection (OCP), undervoltage protection (UVP), catastrophic failure protection (CFP), and fault response settings. No firmware is required for programming, and checksum validation ensures integrity. This capability is explicitly stated in the ISL6388HRTZ "Features" section and confirmed in FN8571 Rev 0.00.
What is the function of the TM pin on the ISL6388HRTZ?
The TM pin on the ISL6388HRTZ is an analog input for connecting an NTC thermistor to enable real-time thermal monitoring. The internal ADC digitizes the thermistor voltage, providing temperature data for both system-level thermal management and integrated compensation of current-sense elements. This compensation improves current measurement accuracy across temperature gradients. The TM pin functionality is detailed in the ISL6388HRTZ electrical characteristics and application sections of FN8571.
Can the ISL6388HRTZ operate in single-phase mode, and under what conditions?
Yes, the ISL6388HRTZ operates in single-phase mode during ultra-low-power states (PSI2 and PSI3), triggered by de-assertion of the PSI# signal from the CPU. In PSI1 mode, it supports programmable 1- or 2-phase operation. Phase dropping and re-adding are fully automatic and preserve transient response. This behavior is defined in the ISL6388HRTZ functional description and transient response sections of FN8571 Rev 0.00.
ISL6388HRTZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VR12, VR12.5
- Voltage - Input:
- 4.5V ~ 14V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.25V ~ 3.04V
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-TQFN (5x5)
ISL6388HRTZ FAQ
1.How can I place an order for ISL6388HRTZ through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6388HRTZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6388HRTZ reliable?
The price and inventory of ISL6388HRTZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6388HRTZ is usually 5 days.
3.What payment methods are accepted for ISL6388HRTZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6388HRTZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6388HRTZ?
ISL6388HRTZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6388HRTZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6388HRTZ?
For technical support, including ISL6388HRTZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6388HRTZ requirements.
6.How does Aetrix verify that ISL6388HRTZ is sourced from the original manufacturer or authorized distributors?
All ISL6388HRTZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6388HRTZ meets industry standards.
7.What is the process for return or replacement of ISL6388HRTZ?
All ISL6388HRTZ units undergo pre-shipment inspection (PSI). If there is an issue with ISL6388HRTZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6388HRTZ part is unused and in its original packaging.
Return procedure for ISL6388HRTZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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