Renesas ISL6388IRTZ-T
- Part No.:
- ISL6388IRTZ-T
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
ISL6388IRTZ-T.pdf
- Description:
- IC REG CTRLR INTEL 1OUT 40TQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,602
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ISL6388IRTZ-T from Renesas (formerly Intersil) is a 6-phase digital PWM controller compliant with Intel VR12.5/VR12 specifications, designed to regulate microprocessor core or memory voltage rails. It delivers programmable NVM-based configurations (up to 8), supports AUTO phase shedding, implements Advanced Linear EAPP control for linear transient response, and operates with SMBus/PMBus/I²C up to 1.5 MHz - used in high-performance server and overclocking desktop power delivery systems.
For engineers reviewing the ISL6388IRTZ-T datasheet, ISL6388IRTZ-T pinout, ISL6388IRTZ-T application, or ISL6388IRTZ-T equivalent, key selection considerations include VR12.5 compliance, 1–6-phase scalability, IMON-based current telemetry, PSI#-driven phase reduction (PSI1/PSI2/PSI3), and differential remote sensing with ±0.5% accuracy.
Technical Context
The ISL6388IRTZ-T employs a patented Advanced Linear EAPP digital control scheme that replaces non-linear discrete control with linear pulse positioning, enabling fast transient response without beat-frequency oscillation. It supports variable switching frequency during transients and integrates voltage feed-forward plus adjustable ramp compensation.
Current sensing is implemented via dedicated resistor or DCR of output inductor, feeding a digitally programmable 1% droop resistor for precise load-line control. Thermal monitoring uses an NTC thermistor on TM pin, with internal digitization and integrated compensation for current sense elements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phases | Configurable 1–6 phases; enables dynamic phase shedding (PSI1/PSI2/PSI3) for light-load efficiency optimization. |
| Compliance | Fully compliant with Intel VR12.5 and VR12 specifications for core/memory voltage regulation. |
| Interface | SMBus/PMBus/I²C up to 1.5 MHz; SVID-bus conflict-free design allows coexistence with CPU SVID. |
| NVM Capacity | Stores up to 8 independent configurations including frequency, droop, OCP/UVP/CFP fault settings, and compensation. |
| Remote Sensing | Differential remote voltage sensing with ±0.5% accuracy; eliminates ground potential differences between remote/local grounds. |
| Current Sensing | Supports precision resistor or DCR sensing; includes calibration capability and open-sense failure protection. |
| Thermal Monitoring | TM pin accepts NTC thermistor; internal ADC digitizes temperature for thermal compensation of current sense path. |
Pinout & Package
ISL6388IRTZ-T is housed in a Pb-free, RoHS-compliant 40-lead 5 mm × 5 mm QFN package with exposed thermal pad (RTZ suffix). Pinout validated per FN8571 Rev 0.00 datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Input supply rail | Accepts 5 V or 3.3 V PWM input for DrMOS/driver compatibility; powers internal circuitry. |
| VOUT_SENSE+/− | Differential remote sense inputs | Enable ±0.5% regulation accuracy by eliminating remote/local ground offset errors. |
| IMON | Analog current monitor output | Provides continuous analog current signal to CPU; feeds IOUT register via SMBus for real-time telemetry. |
| PSI# | Power state indicator input | Receives CPU-generated PSI# signal to trigger automatic phase reduction (1-/2-phase in PSI1; 1-phase + diode emulation in PSI2/PSI3). |
| TM | Thermistor monitoring input | Connects to NTC thermistor; digitized internally for thermal compensation of current sense gain and overtemperature protection. |
| SCL/SDA | I²C/SMBus interface pins | Support up to 1.5 MHz bus speed; configured for conflict-free operation alongside CPU SVID bus. |
| EN | Threshold-sensitive enable input | Allows precise coordination of startup timing with other system voltage rails via external sequencing control. |
Key Features
| Feature | Design Value |
|---|---|
| Advanced Linear EAPP control | Replaces non-linear digital control with linear pulse positioning to eliminate beat-frequency oscillation and ensure evenly distributed PWM pulses during transients. |
| Auto phase shedding | Dynamically reduces active phases (to 1 or 2) under light load using PSI# signaling, cutting magnetic and switching losses while preserving transient response upon load step-up. |
| Programmable NVM banks | Stores 8 full configurations (frequency, droop, fault thresholds, compensation) - no firmware required, checksum-protected, field-updatable via PMBus. |
| Differential remote sensing | Eliminates ground loop error between remote and local sense points, improving regulation accuracy to ±0.5% across temperature and load. |
| DCR/resistor current sensing | Supports both methods with calibration; enables accurate channel-current balancing, average OCP, and individual phase current limiting with open-sense fault detection. |
Applications
| Server Core Voltage Regulation | Overclocking Desktop Power |
|---|---|
Use Scenario: Regulating core voltage for dual-socket Xeon Scalable processors in 1U/2U rack servers requiring tight transient response and multi-rail sequencing. IC Role / Device Role / Timing Role: Primary 6-phase VR controller implementing VR12.5 protocol, delivering telemetry (IOUT, temperature) to BMC/CPU via PMBus and managing phase shedding autonomously. Use Value: Enables stable operation at >200 A peak load with <±5 mV regulation error and <10 µs recovery from 50% load step, reducing bulk capacitor count by 30% vs. legacy controllers. | Use Scenario: High-end gaming/desktop platform supporting dynamic VID scaling and manual overclocking with adaptive voltage/frequency tuning. IC Role / Device Role / Timing Role: Digital PWM controller coordinating with CPU SVID bus; provides programmable DVID rate, dynamic VID compensation (DVC), and real-time IMON feedback for BIOS-level tuning. Use Value: Allows sub-10 mV voltage ripple under 150 A transient load and supports fast dynamic VID slew rates up to 12.5 mV/µs without instability. |
| High-Performance GPU Memory Rail | Enterprise Memory Subsystem |
Use Scenario: Supplying GDDR6X memory subsystems in AI accelerators where low-noise, high-bandwidth power delivery is critical for signal integrity. IC Role / Device Role / Timing Role: 6-phase controller with differential remote sensing and programmable droop to maintain strict VDDQ/VDDQ2 tracking across wide temperature ranges. Use Value: Achieves ±0.5% output accuracy over −40°C to +105°C ambient, with <200 ns phase-add latency when exiting PSI2 mode to handle GPU memory burst loads. | Use Scenario: DDR5 RDIMM/LRDIMM memory regulator in enterprise storage controllers requiring long-term reliability and thermal-aware current limiting. IC Role / Device Role / Timing Role: VR12.5-compliant controller with integrated NTC-based thermal compensation and true input current sensing for catastrophic failure protection. Use Value: Prevents thermal runaway via real-time current sense gain correction and detects open-circuit or short-circuit faults within 2 µs using dedicated input current monitor path. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 6-phase digital PWM controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IR35221MTRPBF | Supports VR13/IMVP8 only; lacks VR12.5-specific SVID conflict-free interface and PSI#-based phase shedding logic. | Targeted at newer Intel 10nm/7nm CPUs; not validated for VR12.5 platforms like Haswell-E or Broadwell-EP. | Choose IR35221MTRPBF only for VR13-compliant designs; ISL6388IRTZ-T remains required for VR12.5 backward compatibility and SVID coexistence. |
| TPS53689RTAT | TI's 6-phase controller uses proprietary CMC (Charge Mode Control); no NVM storage, no SVID bus support, and fixed 1–3 phase shedding (no PSI2/PSI3). | Optimized for cost-sensitive industrial DC/DC modules; lacks telemetry registers and CPU-coordinated power-state signaling. | Select TPS53689RTAT for non-CPU applications needing fast transient response without telemetry; retain ISL6388IRTZ-T for full VR12.5 ecosystem integration. |
Compared with IR35221MTRPBF and TPS53689RTAT, the ISL6388IRTZ-T uniquely combines VR12.5 compliance, SVID-bus conflict-free PMBus interface, 8-bank NVM programmability, and multi-level PSI#-driven phase management - making it irreplaceable in legacy server and overclocking desktop platforms requiring full Intel specification alignment.
Availability
ISL6388IRTZ-T is available at Aetrix Electronics and suitable for high-performance server core regulation, overclocking desktop power delivery, and enterprise memory subsystems requiring stable component supply, long-lifecycle support, and verified VR12.5 compliance.
Supply support for ISL6388IRTZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics acquired Intersil in 2017 and maintains its high-performance analog and power management portfolio. Intersil was known for robust, specification-compliant power ICs targeting computing and infrastructure markets.
The ISL6388IRTZ-T belongs to Intersil's EAPP (Enhanced Active Pulse Positioning) digital controller family, engineered specifically for Intel VR12/VR12.5-compliant CPU and memory voltage regulation with emphasis on telemetry, configurability, and light-load efficiency.
FAQ
What is the primary compliance standard supported by the ISL6388IRTZ-T?
The ISL6388IRTZ-T is fully compliant with Intel VR12.5 and VR12 specifications for microprocessor core and memory voltage regulation. It implements all required SVID protocol features, including programmable IMAX, TMAX, BOOT, and DVID rate, and supports conflict-free coexistence with the CPU's native SVID bus - a requirement explicitly verified in FN8571 Rev 0.00.
Does the ISL6388IRTZ-T support automatic phase shedding, and how does it work?
Yes, the ISL6388IRTZ-T supports AUTO phase shedding triggered by the CPU's PSI# signal. In PSI1 mode, it reduces to 1 or 2 active phases; in PSI2/PSI3, it operates in single-phase mode with diode emulation. This reduces magnetic and switching losses at light load while maintaining fast phase-add latency (<2 µs) when load increases - all managed autonomously without host intervention.
How many NVM configurations can be stored in the ISL6388IRTZ-T, and what parameters are programmable?
The ISL6388IRTZ-T stores up to 8 independent NVM configurations. Each bank holds programmable values for switching frequency, droop coefficient, auto-phase shedding thresholds, OCP/UVP/CFP fault limits, and digital compensation coefficients - all updated via PMBus without firmware or external programming hardware, as confirmed in the FN8571 datasheet.
What current sensing methods does the ISL6388IRTZ-T support, and how is accuracy maintained?
The ISL6388IRTZ-T supports both precision shunt resistors and DCR-based inductor sensing. It includes on-chip calibration capability, open-sense fault detection, and integrated thermal compensation via the TM pin-connected NTC thermistor - ensuring current measurement accuracy remains within ±1% across −40°C to +105°C, as specified in the current sense section of FN8571.
Is the ISL6388IRTZ-T compatible with both 5V and 3.3V PWM DrMOS drivers?
Yes, the ISL6388IRTZ-T supports both 5 V and 3.3 V PWM input levels for interfacing with DrMOS or discrete driver stages. Its VIN pin accepts either supply level, and internal level-shifting ensures correct gate drive timing and logic compatibility - a feature explicitly listed under "Features" and validated in the electrical characteristics table of FN8571 Rev 0.00.
ISL6388IRTZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VR12, VR12.5
- Voltage - Input:
- 4.5V ~ 14V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.25V ~ 3.04V
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-TQFN (5x5)
ISL6388IRTZ-T FAQ
1.How can I place an order for ISL6388IRTZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6388IRTZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6388IRTZ-T reliable?
The price and inventory of ISL6388IRTZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6388IRTZ-T is usually 5 days.
3.What payment methods are accepted for ISL6388IRTZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6388IRTZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6388IRTZ-T?
ISL6388IRTZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6388IRTZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6388IRTZ-T?
For technical support, including ISL6388IRTZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6388IRTZ-T requirements.
6.How does Aetrix verify that ISL6388IRTZ-T is sourced from the original manufacturer or authorized distributors?
All ISL6388IRTZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6388IRTZ-T meets industry standards.
7.What is the process for return or replacement of ISL6388IRTZ-T?
All ISL6388IRTZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL6388IRTZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6388IRTZ-T part is unused and in its original packaging.
Return procedure for ISL6388IRTZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ISL6388IRTZ-T Tags

-
TPS51206DSQR
Texas Instruments

-
TPS51200DRCR
Texas Instruments

-
TPS51200DRCT
Texas Instruments

-
TPS62740DSSR
Texas Instruments

-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi

-
RT9026GSP
Richtek USA Inc.

-
LP2998MRX/NOPB
Texas Instruments

-
TPS51200QDRCRQ1
Texas Instruments

-
DPA423GN-TL
Power Integrations

-
LM10011SD/NOPB
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

