Renesas ISL6446IAZ-T7
- Part No.:
- ISL6446IAZ-T7
- Manufacturer:
- Renesas
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 24-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
ISL6446IAZ-T7.pdf
- Description:
- IC REG TRPL BUCK/LNR SYNC 24QSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,448
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Product details
Overview
ISL6446IAZ-T7 from Renesas Electronics (formerly Intersil) is a triple-output power controller integrating two 180° out-of-phase voltage-mode PWM buck controllers and one linear regulator controller for point-of-load regulation in broadband, DSL, and networking systems. It delivers precise 0.6V reference-based output regulation (±1.5% tolerance), programmable 100kHz–2.5MHz switching frequency, lossless rDS(ON)-based overcurrent protection, and PGOOD monitoring with 46ms delay at 1.4MHz.
For engineers reviewing the ISL6446IAZ-T7 datasheet, ISL6446IAZ-T7 pinout, ISL6446IAZ-T7 application, or ISL6446IAZ-T7 equivalent, key selection considerations include interleaved ripple reduction, prebiased soft-start capability, independent enable/soft-start pins (SS1/EN1, SS2/EN2), dual OCP programming via OCSET1/OCSET2, and compatibility with 4.5–24V input ranges using either VIN- or VCC-supplied bias.
Technical Context
The ISL6446IAZ-T7 implements synchronous buck control using fixed-frequency voltage-mode architecture with independent error amplifiers (88dB DC gain, 15MHz GBWP) and external compensation networks on COMP1/COMP2. Its 180° phase shift between PWM1 and PWM2 reduces input RMS current and input capacitor stress.
It integrates a 5V internal linear regulator (VVCC = 4.5–5.6V across input range), 30µA soft-start current sources per channel, and a transconductance linear controller (gm = 2A/V) driving external PNP or PMOS pass devices. Protection includes latch-off OCP (programmable via 110µA OCSET current source), UVP/OVP (8-cycle and 32-cycle detection), and thermal shutdown at +150°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5–5.5V or 5.5–24V - supports dual-supply configuration: VCC-only (5V ±10%) or VIN-powered internal 5V LDO. |
| Output Regulation Reference | 0.600V ±0.0085V (–40°C to +85°C) - enables precise low-voltage outputs (e.g., 0.6V–5V) with resistor-divider feedback. |
| Switching Frequency Range | 100kHz–2.5MHz - set by RT-to-SGND resistor; higher frequencies enable smaller magnetics but reduce max duty cycle (e.g., 80% at 2.5MHz). |
| Overcurrent Sensing | Lossless rDS(ON) sensing - eliminates sense resistor; trip level set by ROCSET and 110µA internal current source (IOC = 110µA × rDS(ON)). |
| PGOOD Thresholds | PWM outputs: ±10% of nominal; Linear output: ≥75% of nominal - open-drain output asserts after 46ms delay (at 1.4MHz) once all three outputs stabilize. |
| Soft-Start Control | Independent SS1/EN1 and SS2/EN2 pins - 30µA current charges external capacitor; ramp completes at ~3.2V; supports prebiased load startup. |
| Thermal Shutdown | +150°C activation with +20°C hysteresis - disables all gate drivers and resets internal logic until temperature falls below +130°C. |
Pinout & Package
ISL6446IAZ-T7 is housed in a RoHS-compliant 24-lead QSOP package (M24.15 drawing), with exposed pad not electrically connected. Thermal resistance θJA = 75°C/W, θJC = 36°C/W. Pin layout optimized for interleaved layout and separate signal (SGND) and power (PGND) ground routing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BOOT1, BOOT2 | Bootstrap supply for high-side gate drivers | Connect to bootstrap capacitors; referenced to PHASE1/PHASE2; internal diode anode tied to VCC. |
| UGATE1, UGATE2 | High-side N-MOSFET gate drive outputs | Bootstrapped outputs capable of 2.6Ω pull-up / 2Ω pull-down; 25ns rise/fall into 3300pF load. |
| LGATE1, LGATE2 | Low-side N-MOSFET gate drive outputs | Sourced from VCC; 2.6Ω pull-up / 2Ω pull-down; must connect to PGND for proper driver return path. |
| PHASE1, PHASE2 | Switch node connections | Junction of upper MOSFET source, lower MOSFET drain, and output inductor; critical for OCP sensing and layout EMI control. |
| FB1, FB2 | PWM output voltage feedback inputs | Connect to resistor divider from VOUTx to SGND; sets output via 0.6V internal reference; also used for PGOOD and OVP/UVP monitoring. |
| OCSET1, OCSET2 | Overcurrent threshold programming inputs | 110µA current source pulls down through ROCSET to upper MOSFET drain; trip occurs when PHASEx < OCSETx during high-side conduction. |
| SS1/EN1, SS2/EN2 | Per-channel soft-start and enable inputs | 30µA current charges external capacitor for soft-start; <0.85V disables channel; >1.05V enables with hysteresis. |
| LCFB, LCDR | Linear regulator feedback and driver outputs | LCFB sets linear output via 0.595V threshold; LCDR sinks up to 50mA to drive external PNP base or PMOS gate. |
| PGOOD | Open-drain power-good status indicator | Pulled low if any PWM output deviates >±10% or linear output drops <75%; requires external pull-up to 3.3V or 5V. |
| VIN, VCC, SGND, PGND | Power and ground supplies | VIN powers internal LDO (if >5.5V) or connects directly to VCC (if 5V input); SGND and PGND must be routed separately to minimize noise coupling. |
Key Features
| Feature | Design Value |
|---|---|
| 180° Interleaved PWM Operation | Reduces input RMS current by ~30% and cuts input capacitor RMS ripple vs. in-phase operation - lowers cost and size of bulk input capacitance. |
| Prebiased Load Soft-Start | Enables seamless ramp-up from existing output voltage (below or above final target) without overshoot or reverse current - critical for hot-swap and multi-rail sequencing. |
| Voltage Tracking Capability | Independent SS1/EN1 and SS2/EN2 pins allow synchronized or staggered ramp timing - supports controlled power-up sequences for FPGA/DSP core/I/O rails. |
| Lossless Current Sensing | Eliminates dedicated current-sense resistor and associated power loss - improves efficiency and simplifies PCB layout while maintaining accurate OCP at full load. |
| Integrated 5V Bias Regulator | Internal LDO generates stable VCC from VIN (5.5–24V), enabling single-rail system supply; VCC can also accept external 5V ±10% input. |
| Robust Fault Management | Latch-off OCP, hiccup-mode UVP, and OVP with 32-cycle confirmation prevent false triggering while ensuring fast response to sustained faults. |
Applications
| ATX Power Supplies | DSP/ASIC/FPGA Point-of-Load Regulation |
|---|---|
|
Use Scenario: Primary +5V and +3.3V rail generation in desktop/server ATX PSUs with tight ripple and transient requirements. IC Role / Device Role / Timing Role: Dual PWM controller manages interleaved buck stages; linear controller provides auxiliary low-noise bias for analog subsystems. Use Value: 180° phase shift cuts input capacitor RMS current by ~30%, reducing required capacitance and improving reliability under high-load conditions. |
Use Scenario: Independent core and I/O voltage regulation for high-performance DSPs, ASICs, and FPGAs requiring strict sequencing and low-noise supplies. IC Role / Device Role / Timing Role: ISL6446IAZ-T7 delivers tightly regulated, sequenced outputs (e.g., 1.2V core, 2.5V I/O) with programmable soft-start timing and PGOOD coordination. Use Value: Independent SS1/EN1 and SS2/EN2 pins enable precise voltage tracking and staggered startup - prevents latch-up and ensures clean power-on reset. |
| Industrial Networking Equipment | DSL/Broadband Access Systems |
|
Use Scenario: Power management in managed switches, routers, and industrial Ethernet gateways operating in extended temperature environments. IC Role / Device Role / Timing Role: Triple-output controller supplies CPU, PHY, and auxiliary logic rails with robust OCP, UVP, and thermal protection across –40°C to +85°C. Use Value: Latch-off OCP and +150°C thermal shutdown ensure fail-safe operation during cable fault, short-circuit, or ambient overheating events. |
Use Scenario: Multi-rail power for DSLAM line cards, ONTs, and broadband CPE requiring high efficiency and low EMI in space-constrained enclosures. IC Role / Device Role / Timing Role: ISL6446IAZ-T7 integrates two high-efficiency PWMs and a low-noise linear stage to meet stringent spectral mask and thermal limits. Use Value: Programmable 100kHz–2.5MHz switching frequency allows optimization for efficiency (low-freq) or compactness (high-freq), balancing BOM cost and board area. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-output controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6541IRZ-T7 | Single 180° dual-phase PWM controller (no linear regulator); 0.6V reference; 200kHz–1.5MHz range; lacks LCFB/LCDR and PGOOD for linear output. | Only suitable where linear output is unnecessary; cannot replace ISL6446IAZ-T7 in designs requiring auxiliary low-noise bias or analog subsystem supply. | Select only when third output is implemented externally or omitted; verify sequencing and protection coverage matches system requirements. |
| RT8209AZQW | Dual PWM controller (no linear stage); 0.6V reference; 100kHz–1.2MHz; integrated MOSFET drivers but no lossless OCP - requires external sense resistor. | Higher component count due to external current sensing; no support for prebiased startup or voltage tracking; limited thermal margin (TJ max = +125°C). | Consider only for cost-sensitive, non-sequencing applications where linear output is absent and thermal environment is benign. |
Compared with ISL6446IAZ-T7, ISL6541IRZ-T7 omits linear regulation and PGOOD integration for that rail, while RT8209AZQW adds external sensing complexity and lacks prebias support - making ISL6446IAZ-T7 uniquely suited for compact, sequenced, triple-rail systems with analog bias needs.
Availability
ISL6446IAZ-T7 is available at Aetrix Electronics and suitable for ATX power supplies, DSP/ASIC/FPGA point-of-load regulation, and industrial networking equipment requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for ISL6446IAZ-T7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and maintains full technical and manufacturing continuity for the ISL64xx product family. Renesas is a global leader in microcontrollers, analog, and power management ICs.
The ISL6446IAZ-T7 belongs to Renesas' high-density power controller portfolio, designed specifically for multi-rail, high-efficiency DC/DC conversion in broadband infrastructure, networking, and computing applications where interleaving, sequencing, and integrated protection are essential.
FAQ
What input voltage configurations does the ISL6446IAZ-T7 support?
The ISL6446IAZ-T7 supports two distinct input configurations: (1) 4.5–5.5V applied directly to VCC, or (2) 5.5–24V applied to VIN, which powers an internal 5V linear regulator feeding VCC. When using VIN > 5.5V, VCC becomes the regulated 5V output; when using 5V ±10% input, VCC must be externally connected to VIN. Both modes are validated per Table 1 in FN7944 Rev 2.00.
How does the ISL6446IAZ-T7 achieve lossless overcurrent protection?
The ISL6446IAZ-T7 uses the upper MOSFET's rDS(ON) as a current-sense element. A 110µA internal current source pulls down through an external resistor (ROCSET) connected between OCSETx and the upper MOSFET drain. When the PHASEx voltage drops below the OCSETx voltage during high-side conduction, an overcurrent condition is detected. This eliminates the need for a discrete sense resistor, reducing cost and power loss.
Can the ISL6446IAZ-T7 soft-start into a prebiased output voltage?
Yes, the ISL6446IAZ-T7 supports prebiased soft-start on both PWM outputs. When the output voltage is precharged below the target, the upper FET remains off until the SSx/ENx ramp exceeds the output voltage, then ramps seamlessly upward. If prebiased above the target (but below OVP threshold), the output is pulled down after soft-start completion. This behavior is confirmed in Figures 14 and 20 of FN7944 Rev 2.00.
What is the function of the LCFB and LCDR pins on the ISL6446IAZ-T7?
LCFB is the feedback input for the linear regulator, with a 0.595V threshold (–40°C to +85°C). LCDR is an open-drain driver output that sinks up to 50mA to control the base of an external PNP transistor or gate of a PMOS pass device. Together, they implement a programmable positive linear regulator - LCFB sets the output voltage via an external divider, and LCDR provides the active drive.
How is the PGOOD signal generated and delayed on the ISL6446IAZ-T7?
PGOOD asserts high only after all three outputs (PWM1, PWM2, linear) meet their respective thresholds: PWM outputs within ±10% of nominal, linear output ≥75% of nominal. Once satisfied, an internal timer starts with delay tPGOOD = 0.065 / fSW seconds (e.g., 46ms at 1.4MHz). The delay is inversely proportional to switching frequency and cannot be adjusted independently - verified in Electrical Specifications (page 8) and Functional Description (page 12) of FN7944 Rev 2.00.
ISL6446IAZ-T7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 24-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (1)
- Number of Outputs:
- 3
- Frequency - Switching:
- 100kHz ~ 2.6MHz
- Voltage/Current - Output 1:
- Controller
- Voltage/Current - Output 2:
- Controller
- Voltage/Current - Output 3:
- Controller
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-QSOP
ISL6446IAZ-T7 FAQ
1.How can I place an order for ISL6446IAZ-T7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6446IAZ-T7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6446IAZ-T7 reliable?
The price and inventory of ISL6446IAZ-T7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6446IAZ-T7 is usually 5 days.
3.What payment methods are accepted for ISL6446IAZ-T7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6446IAZ-T7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6446IAZ-T7?
ISL6446IAZ-T7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6446IAZ-T7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6446IAZ-T7?
For technical support, including ISL6446IAZ-T7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6446IAZ-T7 requirements.
6.How does Aetrix verify that ISL6446IAZ-T7 is sourced from the original manufacturer or authorized distributors?
All ISL6446IAZ-T7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6446IAZ-T7 meets industry standards.
7.What is the process for return or replacement of ISL6446IAZ-T7?
All ISL6446IAZ-T7 units undergo pre-shipment inspection (PSI). If there is an issue with ISL6446IAZ-T7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6446IAZ-T7 part is unused and in its original packaging.
Return procedure for ISL6446IAZ-T7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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