Renesas ISL6505CB

Overview

ISL6505CB from Intersil is a multiple linear power controller with ACPI control interface, designed for motherboard-level power management in ATX-compliant microprocessor systems. It integrates three linear regulators (3.3VDUAL/3.3VSB, 1.2VVID, VOUT1), one dual-mode 5VDUAL switch controller, undervoltage monitoring, thermal shutdown, and S3/S5 state logic - all in a 20-pin wide-body SOIC package. It delivers precise voltage planes for south bridge, PCI slots, VID circuitry, and LAN/Ethernet subsystems.

For engineers reviewing the ISL6505CB datasheet, ISL6505CB pinout, ISL6505CB application, or ISL6505CB equivalent, this device requires attention to its ACPI sleep-state sequencing (S0–S5), external pass transistor selection (NPN/NFET/PFET), soft-start capacitor sizing (0.1µF typical), and EN5/LAN pin configuration dependencies for 5VDUAL and VOUT1 behavior.

Technical Context

The ISL6505CB implements four independent regulated outputs: 3.3VDUAL/3.3VSB (linear, NPN/NFET-switched), 5VDUAL (NMOS/PMOS-switched with EN5-selectable S5 behavior), 1.2VVID (active-only linear regulator powered from 3V3), and VOUT1 (1.2–1.5V programmable via FB1/DR1 with LAN-selectable on/off timing). Its control architecture uses digital S3/S5 inputs with internal deglitching (2µs) and state transition blocking (no S4/S5→S3).

Undervoltage detection is applied to all four outputs plus monitored ATX rails (3V3, 5V), with centralized FAULT reporting and temperature monitoring (125°C fault, 155°C shutdown). Soft-start is implemented via an internal 10µA current source charging an external CSS capacitor, enabling controlled ramp-up of 3.3VDUAL/3.3VSB and VOUT1 before activating 1.2VVID and 5VDUAL.

Key Specifications

Pinout & Package

ISL6505CB is housed in a 20-lead wide-body SOIC package (JEDEC MS-013, package drawing M20.3), with exposed pad not present. Pin functions are electrically identical to the QFN variant but mapped to SOIC pinout.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multiple-output ACPI power controller applications.

Compared with ISL6505CR, the ISL6505CB offers identical electrical behavior in SOIC form for legacy-compatible layouts; compared with RT8205A, it provides dedicated 1.2VVID regulation and greater flexibility in pass device selection, at the cost of higher external component count.

Availability

ISL6505CB is available at Aetrix Electronics and suitable for desktop motherboard design, ACPI-compliant power sequencing, and embedded computing platforms requiring stable component supply across extended production lifecycles.

Supply support for ISL6505CB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Intersil Corporation (now part of Renesas Electronics) is a U.S.-based semiconductor company specializing in precision analog and power management ICs for computing, industrial, and communications markets.

The ISL6505CB belongs to Intersil's ACPI-compliant power controller product line, engineered specifically to replace discrete regulator + logic combinations in ATX motherboard power trees while ensuring strict compliance with ACPI 2.0+ sleep/wake state definitions.

FAQ

What is the primary function of the ISL6505CB in a motherboard power system?

The ISL6505CB serves as a centralized multiple linear power controller that manages four critical voltage planes - 3.3VDUAL/3.3VSB, 5VDUAL, 1.2VVID, and programmable VOUT1 - while enforcing ACPI-defined S0–S5 sleep-state transitions. It replaces discrete regulators and sequencing logic, using external pass transistors (NPN/NFET/PMOS) to deliver efficient, state-aware power to south bridge, PCI, LAN, and processor VID circuitry. Its integration reduces component count and ensures deterministic power-up/down timing.

How does the EN5 pin affect 5VDUAL behavior in S5 sleep state?

The EN5 pin directly controls whether the 5VDUAL output remains active or shuts down during S4/S5 (soft-off) state. When EN5 is tied high or left open, 5VDUAL stays on in S5 - useful for peripherals requiring standby power like USB wakeup. When EN5 is tied low (GND), 5VDUAL is disabled in S5, minimizing system standby consumption. This behavior is explicitly defined in Table 1 of the ISL6505CB datasheet and is independent of S3/S5 pin states during S4/S5 entry.

Can the ISL6505CB generate the 1.2VVID output in sleep states?

No, the ISL6505CB generates the 1.2VVID output exclusively during active states (S0, S1/S2). The internal 1.2VVID linear regulator is powered from the 3V3 pin and is intentionally disabled in all sleep states (S3, S4/S5) to reduce quiescent power. Its output is monitored for undervoltage, and VID_PG asserts only after the 1.2VVID rail reaches 90% of target during active-state soft-start - confirming proper VID circuitry readiness before processor boot.

What external components are mandatory for ISL6505CB operation?

Mandatory external components for ISL6505CB include: (1) a 0.1µF ceramic capacitor on SS pin for soft-start timing; (2) resistor divider on FB1 to set VOUT1 voltage (1.2–1.5V); (3) external NPN transistor driven by 3V3DLSB for 3.3VDUAL regulation in sleep states; (4) external NFET driven by DR1 for VOUT1; (5) external NMOS/PMOS transistors for 3.3VDUAL and 5VDUAL switching; and (6) 10kΩ pull-up on VID_PG. No bypass capacitors are listed as mandatory in the datasheet, but standard practice applies.

How does the ISL6505CB respond to loss of ATX 3.3V or 5V input during active operation?

If either ATX 3.3V (on 3V3 pin) or ATX 5V (on 5V pin) falls below its undervoltage threshold during S0/S1/S2, the ISL6505CB forces an immediate transition to S5 sleep state and asserts the FAULT pin high. This action protects downstream circuitry by removing regulated outputs while signaling the fault to the system controller. Recovery requires restoring the failed rail above its rising threshold, cycling 5VSB, or pulling SS low to reset latched conditions - as detailed in the Fault Protection section of the ISL6505CB datasheet.