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Renesas ISL6505CB-T
- Part No.:
- ISL6505CB-T
- Manufacturer:
- Renesas
- Category:
- Power Supply Controllers, Monitors
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
ISL6505CB-T.pdf
- Description:
- IC MULTIPLE POWER CTRLR 20-SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,970
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Product details
Overview
ISL6505CB-T from Intersil is a multiple linear power controller with ACPI control interface, designed for motherboard-level power management in ATX-compliant microprocessor systems. It integrates four regulated outputs - 3.3VDUAL/3.3VSB (3.3V), 5VDUAL (5V), 1.2VVID, and programmable VOUT1 (1.2–1.5V) - with digital S3/S5 state control, undervoltage monitoring, thermal shutdown, and fault reporting via open-drain FAULT pin.
For engineers reviewing the ISL6505CB-T datasheet, ISL6505CB-T pinout, ISL6505CB-T application, or ISL6505CB-T equivalent, this device serves as a core ACPI-compliant power sequencer for legacy desktop/server motherboards requiring coordinated sleep-state voltage delivery, precise soft-start timing, and centralized fault signaling across multiple rail domains.
Technical Context
The ISL6505CB-T implements dual-mode linear regulation for 3.3VDUAL/3.3VSB: using external NPN in S3/S4/S5 states and N-channel MOSFET in S0/S1/S2 states, enabling low-loss active operation and robust standby biasing. Its 5VDUAL output switches between ATX 5V (active) and 5VSB (S3/S5) via NMOS/PMOS control, with EN5 pin selecting S5 behavior.
VOUT1 is user-programmable (1.2–1.5V) via FB1/DR1 and mode-selectable via LAN pin (always-on for 10/100 LAN; active-only for Gigabit Ethernet); the 1.2VVID regulator operates exclusively in S0/S1/S2 and powers processor VID circuitry, with dedicated VID_PG and VID_CT timing control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count | Four independent rails: 3.3VDUAL/3.3VSB, 5VDUAL, 1.2VVID, VOUT1 (1.2–1.5V) |
| ACPI State Support | Full S0–S5 state sequencing with S3/S5 digital inputs and EN5/LAN configuration pins |
| Regulation Accuracy | ±2.0% over temperature for all outputs - ensures stable voltage delivery under thermal stress |
| Soft-Start Control | Internal 10µA current source + external CSS capacitor (≥5nF) enables controlled ramp-up and transition timing |
| Fault Reporting | Open-drain FAULT pin asserts high on any UV event (outputs or ATX 3.3V/5V), overtemperature (>125°C), or VID failure |
| Thermal Protection | Overtemperature shutdown at 155°C (typical); fault flag asserted at 125°C (typical) |
| Package | 20-pin wide-body SOIC (M20.3), 0°C to +70°C ambient operating range |
Pinout & Package
ISL6505CB-T uses a 20-pin wide-body SOIC package (JEDEC MS-013, pkg drawing M20.3), with GND-connected exposed pad not present (unlike QFN variant). Pin functions are electrically identical to ISL6505CR but mapped to SOIC layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB1 (Pin 1) | VOUT1 feedback input | Compares external resistor divider voltage to 0.8V internal reference to regulate 1.2–1.5V output |
| DR1 (Pin 2) | VOUT1 gate driver output | Sinks up to 10mA to drive external NFET gate; draws current from 3V3DL rail |
| 3V3DLSB (Pin 3) | 3.3VDUAL/3.3VSB NPN base drive | Drives external NPN transistor base during S3/S4/S5 to regulate 3.3V from 5VSB |
| 3V3DL (Pin 4) | 3.3VDUAL/3.3VSB output node | Delivers regulated 3.3V in sleep states; passes ATX 3.3V directly in active states via external NFET |
| 1V2VID (Pin 5) | 1.2V VID circuitry supply | Provides up to 180mA at ±2.0% accuracy only in S0/S1/S2; shut down in all sleep states |
| 3V3 (Pin 6) | ATX 3.3V monitor & VID input source | Supplies current to 1V2VID regulator; monitored for UV (2.65–3.0V window) to trigger S5 transition |
| 5V (Pin 7) | ATX 5V monitor | Monitored for UV (4.0–4.5V window); drop below threshold forces S5 entry regardless of S3/S5 state |
| EN5 (Pin 8) | 5VDUAL S5 enable control | Logic high/open keeps 5VDUAL active in S5; logic low shuts it down - determines S4/S5 behavior per Table 1 |
| S3 (Pin 9) | ACPI S3 sleep state input | Internal 50µA pull-up to 5VSB; deglitched (2µs); 200µs delay before state transition to prevent noise-induced false triggers |
| S5 (Pin 10) | ACPI S5 sleep state input | Internal 50µA pull-up to 5VSB; deglitched (2µs); combined with S3 defines full ACPI state machine (S0–S5) |
| GND (Pin 11) | Signal ground reference | All voltages referenced to this pin; required for accurate UV detection and regulation stability |
| FAULT (Pin 12) | Centralized fault reporting output | Open-drain CMOS output pulled to 5VSB on fault (UV, overtemp); no external pull-down needed |
| DLA (Pin 13) | Active-state gate drive enable | Open-collector output; pulls up to 12V via 1kΩ resistor to turn on external NFETs for 3.3V/5V switching in S0/S1/S2 |
| 5VDLSB (Pin 14) | 5VDUAL PMOS/PNP gate drive | Drives gate/base of external PMOS or PNP to connect 5VSB to 5VDUAL during S3 and optionally S5 (if EN5 = high) |
| 5VDL (Pin 15) | 5VDUAL output node | Delivers 5V via external NMOS in active states; monitored for UV (4.10V rising threshold) |
| LAN (Pin 16) | VOUT1 operational mode select | 10µA pull-up to 5VSB; high/open enables always-on 10/100 LAN mode; low enables active-only Gigabit mode |
| VID_PG (Pin 18) | 1.2VVID power-good indicator | Open-collector output; goes high after VID_CT capacitor charges and 1.2V reaches 90% of target - signals VID readiness |
| VID_CT (Pin 19) | VID power-good timing capacitor | Connects to GND; sets delay between 1.2VVID reaching regulation and VID_PG assertion (via internal 10µA charge) |
| 5VSB (Pin 20) | Main bias supply input | Accepts +5V ±5% ATX 5VSB; powers entire IC, provides POR reference (4.0–4.5V rising threshold), and pull-up source for S3/S5/EN5/LAN |
Key Features
| Feature | Design Value |
|---|---|
| ACPI-compliant multi-rail control | Hardware-enforced S0–S5 state transitions with illegal transition blocking (e.g., S4/S5 → S3 prohibited) |
| Dual-path 3.3VDUAL/3.3VSB regulation | External NPN for low-quiescent sleep regulation; external NFET for zero-drop active delivery - minimizes conduction loss |
| Configurable 5VDUAL S5 behavior | EN5 pin selects whether 5VDUAL remains active (EN5 = high/open) or shuts down (EN5 = low) in S5 - supports USB wake vs. deep-sleep design choices |
| User-programmable VOUT1 | 1.2–1.5V output set by external resistor divider on FB1; LAN pin configures availability across ACPI states without changing voltage |
| Integrated fault coordination | Single FAULT pin reports undervoltage on any output or monitored ATX rail (3.3V/5V), plus overtemperature - simplifies system-level error handling |
Applications
| Desktop Motherboard Power Management | Server Board ACPI Sequencing |
|---|---|
|
Use Scenario: ATX-compliant desktop motherboard requiring coordinated S0–S5 power delivery to south bridge, PCI slots, USB peripherals, and LAN controllers. IC Role / Device Role / Timing Role: Centralized ACPI power controller managing 3.3VDUAL/3.3VSB, 5VDUAL, 1.2VVID, and VOUT1 with hardware state-machine enforcement and soft-start synchronization. Use Value: Eliminates discrete logic and multiple regulators; reduces BOM count and PCB area while guaranteeing compliant sleep/wake timing per ACPI specification. |
Use Scenario: Dual-processor server board needing reliable wake-from-S5 capability, USB device charging during S3, and VID-circuitry isolation during suspend. IC Role / Device Role / Timing Role: Multi-output sequencer enforcing strict voltage sequencing, fault propagation, and state-dependent rail enablement across redundant ATX supplies. Use Value: Ensures deterministic power-up/down across complex multi-rail topologies; prevents brownout-induced firmware hangs during state transitions. |
| Laptop Docking Station Power | Embedded Industrial Controller |
|
Use Scenario: Docking station supplying auxiliary 3.3V/5V rails to connected peripherals while maintaining host system sleep integrity. IC Role / Device Role / Timing Role: Auxiliary power manager delivering 3.3VDUAL/3.3VSB and 5VDUAL to USB/PCIe add-in cards, with EN5-configurable S5 retention for wake-on-LAN support. Use Value: Enables persistent peripheral power during host S5 without violating ATX spec; avoids need for separate always-on LDOs. |
Use Scenario: Fanless industrial controller requiring thermal-aware power management and fail-safe shutdown under overtemperature conditions. IC Role / Device Role / Timing Role: Fault-integrated power supervisor providing 125°C fault flagging and 155°C unconditional shutdown - protects downstream logic from thermal damage. Use Value: Replaces discrete thermal sensor + comparator + reset generator; reduces component count and improves response time to thermal events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multiple-output ACPI power controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6520CRZ-T | QFN-24 package; adds 2.5V rail and enhanced VID support; higher integration but no SOIC option | Targets newer ATX12V 2.x designs with tighter VID tolerance; requires PCB redesign due to different pinout and footprint | Choose ISL6520CRZ-T only when upgrading to 2.5V rail support and accepting QFN-only assembly; not drop-in compatible with ISL6505CB-T |
| TPS51100PWR | TI dual-output controller (3.3V/5V only); no VID or VOUT1; supports only S0/S3/S5, lacks S1/S2 granularity | Designed for cost-sensitive embedded boards without processor VID requirements or Gigabit LAN sequencing needs | Choose TPS51100PWR for simplified two-rail applications where ACPI state fidelity and programmable VOUT1 are unnecessary |
Compared with ISL6505CB-T, ISL6520CRZ-T offers expanded rail count and VID capability but mandates QFN assembly and layout change, while TPS51100PWR reduces complexity and cost at the expense of ACPI state resolution and multi-rail flexibility - making ISL6505CB-T optimal for legacy ATX motherboard reuse and precise S0–S5 compliance.
Availability
ISL6505CB-T is available at Aetrix Electronics and suitable for desktop motherboard design, server board power sequencing, docking station auxiliary power, and industrial controller thermal supervision requiring stable component supply and long-lifecycle support.
Supply support for ISL6505CB-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) specialized in high-performance analog and power management ICs for computing, communications, and industrial markets.
The ISL6505CB-T belongs to Intersil's ACPI Power Controller product line, engineered specifically for ATX-compliant motherboard power sequencing with hardware-enforced S0–S5 state transitions and integrated fault coordination.
FAQ
What is the operating temperature range for the ISL6505CB-T?
The ISL6505CB-T is specified for an ambient operating temperature range of 0°C to +70°C. Its junction temperature may reach up to 125°C under normal operation and will initiate fault reporting at 125°C (typical), with unconditional shutdown occurring at 155°C (typical). Thermal resistance θJA is 65°C/W for the SOIC package, requiring appropriate PCB copper pour for sustained loads.
How does the ISL6505CB-T handle undervoltage on monitored ATX rails?
When either the ATX 3.3V (Pin 6) or 5V (Pin 7) rail drops below its falling UV threshold - 2.65V for 3.3V and 4.0V for 5V - the ISL6505CB-T forces an immediate transition to S5 sleep state and asserts the FAULT pin high. This behavior is independent of S3/S5 pin states and ensures system-level power integrity even if sleep control signals are compromised.
Can the ISL6505CB-T's VOUT1 output be disabled in all ACPI states?
No - VOUT1 behavior is determined by the LAN pin and ACPI state. With LAN = GND (Gigabit Ethernet mode), VOUT1 is active only in S0/S1/S2. With LAN = high/open (10/100 LAN mode), VOUT1 remains active across S0–S5. There is no configuration that disables VOUT1 in all states; however, pulling SS low forces full shutdown including VOUT1.
What is the purpose of the DLA pin on the ISL6505CB-T?
The DLA (Drive Logic Active) pin is an open-collector output used exclusively in active states (S0/S1/S2) to enable external NFETs that switch ATX 3.3V and 5V into the 3.3VDUAL/3.3VSB and 5VDUAL outputs. It is pulled high via an external 1kΩ resistor to 12V, turning on the FETs only when the system is awake - ensuring zero conduction loss during sleep.
Is the ISL6505CB-T still recommended for new designs?
No - the ISL6505CB-T is marked "OBSOLETE PRODUCT" in the official datasheet (FN9109 Rev 3.00) with "NO RECOMMENDED REPLACEMENT." While functional and supported for legacy repair and continuity, new designs should evaluate modern alternatives such as ISL6520 or Renesas' ZLxxxx series for improved efficiency, smaller footprint, and extended feature sets.
ISL6505CB-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Applications:
- Power Supply Controller/Monitor
- Voltage - Input:
- -
- Voltage - Supply:
- 4.75V ~ 5.25V
- Current - Supply:
- 6 mA
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SOIC
ISL6505CB-T FAQ
1.How can I place an order for ISL6505CB-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6505CB-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6505CB-T reliable?
The price and inventory of ISL6505CB-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6505CB-T is usually 5 days.
3.What payment methods are accepted for ISL6505CB-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6505CB-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6505CB-T?
ISL6505CB-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6505CB-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6505CB-T?
For technical support, including ISL6505CB-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6505CB-T requirements.
6.How does Aetrix verify that ISL6505CB-T is sourced from the original manufacturer or authorized distributors?
All ISL6505CB-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6505CB-T meets industry standards.
7.What is the process for return or replacement of ISL6505CB-T?
All ISL6505CB-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL6505CB-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6505CB-T part is unused and in its original packaging.
Return procedure for ISL6505CB-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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