Renesas ISL6505CR-T
- Part No.:
- ISL6505CR-T
- Manufacturer:
- Renesas
- Category:
- Power Supply Controllers, Monitors
- Package:
- 20-VQFN Exposed Pad
- Datasheet:
-
ISL6505CR-T.pdf
- Description:
- IC MULTIPLE POWER CTRLR 20-QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL6505CR-T from Intersil is a quad-output ACPI-compliant linear power controller for ATX motherboard power management, integrating three linear regulators (3.3VDUAL/3.3VSB, 1.2VVID, VOUT1) and one dual-mode switching controller (5VDUAL), with ±2.0% output regulation over temperature, active/sleep state control via S3/S5 pins, and fault reporting via open-drain FAULT pin - used to power south bridge, PCI slots, VID circuitry, and LAN subsystems in desktop/microprocessor systems.
For engineers reviewing the ISL6505CR-T datasheet, ISL6505CR-T pinout, ISL6505CR-T application, or ISL6505CR-T equivalent, key selection considerations include its 20-pin QFN 5×5 mm package, ACPI S0–S5 state sequencing, external pass transistor requirements (NPN/NFET/PFET), 0°C to 70°C operating range, and integrated undervoltage monitoring across all four outputs with centralized FAULT signaling.
Technical Context
The ISL6505CR-T implements state-aware power control using two digital inputs (S3, S5) to select among ACPI S0/S1/S2 (active), S3 (suspend-to-RAM), and S4/S5 (suspend-to-disk/soft-off) modes. Its architecture separates regulation paths: 3.3VDUAL/3.3VSB uses an external NPN in sleep states and NFET in active states; 5VDUAL switches between ATX 5V (active) and 5VSB (S3/S5) via NMOS/PMOS; 1.2VVID operates only in S0/S1/S2 and draws from 3V3; VOUT1 (1.2–1.5V) is user-programmable and LAN-mode-selectable.
It integrates analog monitoring (5V, 3V3, 5VSB POR and UV thresholds), thermal shutdown at 155°C, soft-start via external CSS capacitor, and fault latching behavior that resets only on 5VSB cycling or SS pin assertion - with timing-critical transitions including 200 µs S3 delay and 42–64 ms active-state assessment after UV recovery.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count | Four regulated outputs: 3.3VDUAL/3.3VSB, 5VDUAL, 1.2VVID, VOUT1 (1.2–1.5V) |
| Regulation Accuracy | ±2.0% over temperature for all outputs - ensures stable voltage delivery to sensitive logic and interface circuits |
| Operating Temperature | 0°C to 70°C ambient - validated for commercial motherboard environments without extended thermal derating |
| Package | 20-lead QFN 5×5 mm (JEDEC MO-220 L20.5x5) - near chip-scale footprint enabling high-density PCB layout |
| Supply Current | 6 mA nominal, 4 µA shutdown - low quiescent draw preserves 5VSB standby budget |
| UV Detection Thresholds | 5V: 4.10 V rising / 4.15 V falling; 3V3: 2.93 V rising / 2.78 V falling; FB1: 1.2 V rising - precise fault triggering aligned with ATX spec margins |
| Soft-Start Control | 10 µA internal current source + external CSS capacitor - enables controlled ramp-up of multiple outputs to prevent inrush-induced rail collapse |
Pinout & Package
ISL6505CR-T uses a 20-lead QFN 5×5 mm package (JEDEC MO-220 L20.5x5) with exposed thermal pad tied to GND. Pin numbering follows top-view orientation; QFN pin mapping differs from SOIC but shares identical signal functions per datasheet Figure 6.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB1 (Pin 18) | VOUT1 feedback input | Analog comparator reference node for 1.2–1.5V programmable regulator; monitors external resistor divider against 0.8V internal reference |
| DR1 (Pin 19) | VOUT1 gate driver output | 10 mA sink/source capable NFET gate driver - directly controls external pass FET sourcing from 3V3DL |
| 3V3DLSB (Pin 20) | 3.3VDUAL/3.3VSB NPN base drive | Drives base of external NPN transistor during S3/S4/S5 sleep states to regulate 3.3V output from 5VSB |
| 3V3DL (Pin 1) | 3.3VDUAL/3.3VSB output node | Main regulated output node - connected to external NFET drain in active state, monitored for UV events |
| 1V2VID (Pin 2) | 1.2V VID circuitry supply | Internal linear regulator output active only in S0/S1/S2; delivers up to 180 mA to processor VID logic |
| 3V3 (Pin 3) | ATX 3.3V input monitor | Input for 3.3V rail monitoring and as current source for 1V2VID regulator - not a power output |
| EN5 (Pin 5) | 5VDUAL S5 enable control | Digital input determining whether 5VDUAL remains on (open/high) or shuts down (GND) during S5 state |
| 5V (Pin 4) | ATX 5V input monitor | Monitored only for UV detection - no current sourcing; used to trigger S5 transition if voltage drops below 4.15 V |
| S3 / S5 (Pins 6 / 7) | ACPI state selection inputs | De-glitched digital inputs with 50 µA pull-up to 5VSB - define S0/S1/S2, S3, or S4/S5 mode per truth table |
| LAN (Pin 13) | VOUT1 operational mode select | Selects Gigabit Ethernet (GND = active-only) or 10/100 LAN (open/5V = always-on) behavior for VOUT1 regulator |
| FAULT (Pin 9) | Centralized fault reporting output | Open-drain CMOS output pulled to 5VSB during any UV, overtemperature (>140°C), or internal regulator fault |
| SS (Pin 14) | Soft-start timing and shutdown control | Connects to external capacitor for ramp control; pulling below 0.8 V forces immediate shutdown and FAULT reset |
| VID_PG (Pin 15) | 1.2VVID power-good indicator | Open-collector output signaling 1V2VID regulation achieved - requires external 10 kΩ pull-up to 1V2VID |
| VID_CT (Pin 16) | VID power-good delay timing | Connects to external capacitor to set delay before VID_PG asserts - ensures stable 1.2VVID before system release |
| 5VDL (Pin 12) | 5VDUAL output node | Main switching output node - driven by external NMOS in active state, monitored for UV at 4.10 V rising threshold |
| 5VDLSB (Pin 11) | 5VDUAL S3/S5 gate drive | Drives gate of external PFET or PNP to connect 5VSB to 5VDUAL output during S3 and optionally S5 |
| DLA (Pin 10) | Active-state gate drive enable | Open-collector output pulled to ATX 12V via 1 kΩ resistor - enables NFETs for 3.3VDUAL and 5VDUAL in active states |
| 5VSB (Pin 17) | Bias supply input | Main IC bias source - powers internal circuitry and provides base current for external NPN; monitored for POR at 4.3 V rising |
| GND (Pin 8) | Signal ground reference | Common return for all analog and digital signals; bottom thermal pad must be connected to GND plane for thermal performance |
Key Features
| Feature | Design Value |
|---|---|
| ACPI S0–S5 State Sequencing | Hardware-enforced state transitions with 200 µs S3 delay and illegal S4→S3 blocking - eliminates software timing errors in sleep/wake sequences |
| Multi-Path 3.3VDUAL Regulation | Dynamic topology selection: NPN-based linear regulation from 5VSB in sleep states vs. NFET pass-through from ATX 3.3V in active states - minimizes conduction loss where possible |
| Programmable VOUT1 with Mode Select | User-configurable 1.2–1.5V output via resistor divider, plus LAN pin selection for always-on (10/100) or active-only (Gigabit) operation - supports dual Ethernet PHY requirements |
| Centralized Fault Reporting | Single FAULT pin reports UV on any output or monitored rail (3V3, 5V, 5VSB), overtemperature (>140°C), or internal regulator failure - simplifies system-level fault handling |
| Thermal Shutdown with Hysteresis | Unconditional shutdown at 155°C junction temperature, with automatic recovery only after full power cycle - prevents thermal runaway in enclosed chassis |
Applications
| Desktop Motherboard Power Management | ACPI-Compliant Sleep/Wake Sequencing |
|---|---|
Use Scenario: Regulating auxiliary power rails on ATX-compliant desktop motherboards supporting Intel/AMD microprocessors. IC Role / Device Role / Timing Role: Primary ACPI power controller managing 3.3VDUAL/3.3VSB, 5VDUAL, 1.2VVID, and VOUT1 outputs with synchronized soft-start and state-aware switching. Use Value: Eliminates need for discrete supervisor ICs and discrete linear regulators - reduces BOM count and improves timing consistency across sleep/wake transitions. |
Use Scenario: Enforcing correct voltage sequencing and timing during S3 (suspend-to-RAM) and S4/S5 (hibernate/soft-off) transitions. IC Role / Device Role / Timing Role: Hardware state machine implementing ACPI-defined voltage enable/disable order, UV response delays, and deglitched S3/S5 inputs. Use Value: Guarantees compliant behavior without firmware intervention - critical for OS-level suspend/resume reliability and BIOS compatibility. |
| South Bridge & PCI Slot Power | LAN/Ethernet Subsystem Power |
Use Scenario: Supplying stable 3.3VDUAL/3.3VSB to south bridge logic and PCI slot auxiliary power in both active and sleep states. IC Role / Device Role / Timing Role: Dual-path linear regulator delivering 3.3V from either ATX 3.3V (S0–S2) or 5VSB (S3–S5) with seamless handoff and UV monitoring. Use Value: Maintains peripheral functionality during S3 while minimizing standby current - meets ATX specification requirements for auxiliary rail retention. |
Use Scenario: Powering 10/100 or Gigabit Ethernet PHYs requiring either always-on or active-state-only 1.2–1.5V supply. IC Role / Device Role / Timing Role: Programmable VOUT1 regulator with LAN pin mode selection controlling output availability across ACPI states. Use Value: Single IC supports both legacy and modern Ethernet implementations - avoids board redesign when upgrading NIC capabilities. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail ACPI power controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6520CRZ-T | Higher integration: includes integrated MOSFET drivers and enhanced thermal monitoring; supports wider input voltage range (up to 12V). | Targeted at newer ATX12V 2.x designs with higher current demands; lacks direct 1.2VVID regulator - requires external VID solution. | Choose ISL6520CRZ-T for next-gen platforms needing higher drive strength and broader input tolerance, but verify VID implementation compatibility. |
| RT8205AZQW | Single-chip solution with integrated NFETs for 3.3VDUAL and 5VDUAL; no external pass transistor required; lower quiescent current (2.5 mA). | Designed for cost-sensitive, space-constrained embedded motherboards; does not support S4/S5 state retention for VOUT1 - limited to S0–S3 operation. | Choose RT8205AZQW when reducing external component count and board area is prioritized over full S4/S5 LAN mode flexibility. |
Compared with ISL6505CR-T, ISL6520CRZ-T offers greater integration and thermal robustness but removes dedicated 1.2VVID regulation, while RT8205AZQW eliminates external FETs at the cost of reduced ACPI state coverage - making ISL6505CR-T optimal for legacy ATX designs requiring precise S0–S5 compliance with minimal external components beyond pass transistors.
Availability
ISL6505CR-T is available at Aetrix Electronics and suitable for desktop motherboard design, ACPI-compliant power sequencing, and microprocessor auxiliary rail regulation requiring stable component supply across commercial temperature grades and long-lifecycle production programs.
Supply support for ISL6505CR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) is a U.S.-based semiconductor company specializing in precision analog and power management ICs for computing, industrial, and communications markets.
The ISL6505 product line was designed specifically for ACPI-compliant ATX motherboard power architectures, delivering coordinated multi-rail regulation, state-aware switching, and centralized fault monitoring in a single compact package.
FAQ
What is the operating temperature range for the ISL6505CR-T?
The ISL6505CR-T is rated for 0°C to 70°C ambient operating temperature, matching commercial-grade ATX motherboard requirements. Its thermal shutdown activates at 155°C junction temperature, and the QFN package's θJA of 35°C/W enables reliable operation under typical airflow conditions without forced cooling.
How does the ISL6505CR-T handle 3.3VDUAL/3.3VSB regulation in different ACPI states?
In S0–S2 (active), the ISL6505CR-T uses an external NFET to connect ATX 3.3V directly to the 3.3VDUAL/3.3VSB node; in S3–S5 (sleep), it drives an external NPN transistor from 5VSB to regulate the same node. This dual-path approach minimizes losses in active mode while maintaining standby capability - a core feature of the ISL6505CR-T architecture.
Can the ISL6505CR-T be used without external pass transistors?
No - the ISL6505CR-T requires external pass devices: an NPN for 3.3VDUAL/3.3VSB in sleep states, NMOS/PMOS for 5VDUAL, and NFET for VOUT1. It contains no integrated power switches. All regulated outputs depend on correctly selected and biased external transistors, as specified in the ISL6505CR-T datasheet Figures 2 and 3.
What triggers the FAULT pin on the ISL6505CR-T?
The FAULT pin on the ISL6505CR-T goes high (pulled to 5VSB) during undervoltage on any output (3.3VDUAL, 5VDUAL, 1.2VVID, VOUT1) or monitored rail (3V3, 5V, 5VSB), overtemperature (>140°C), or internal regulator fault. It remains asserted until the condition clears and the IC completes a valid soft-start sequence or receives a 5VSB power cycle.
Is the ISL6505CR-T RoHS compliant?
Yes - the ISL6505CR-T is offered in Pb-free plus anneal packaging (RoHS compliant), with 100% matte tin plate termination and materials compatible with both SnPb and lead-free soldering processes, as confirmed in FN9109 Rev 3.00 Note 1.
ISL6505CR-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 20-VQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Applications:
- Power Supply Controller/Monitor
- Voltage - Input:
- -
- Voltage - Supply:
- 4.75V ~ 5.25V
- Current - Supply:
- 6 mA
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-QFN (5x5)
ISL6505CR-T FAQ
1.How can I place an order for ISL6505CR-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6505CR-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6505CR-T reliable?
The price and inventory of ISL6505CR-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6505CR-T is usually 5 days.
3.What payment methods are accepted for ISL6505CR-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6505CR-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6505CR-T?
ISL6505CR-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6505CR-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6505CR-T?
For technical support, including ISL6505CR-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6505CR-T requirements.
6.How does Aetrix verify that ISL6505CR-T is sourced from the original manufacturer or authorized distributors?
All ISL6505CR-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6505CR-T meets industry standards.
7.What is the process for return or replacement of ISL6505CR-T?
All ISL6505CR-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL6505CR-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6505CR-T part is unused and in its original packaging.
Return procedure for ISL6505CR-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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