Renesas ISL6506CBZ-T
- Part No.:
- ISL6506CBZ-T
- Manufacturer:
- Renesas
- Category:
- Power Supply Controllers, Monitors
- Package:
- 8-SOIC (0.154", 3.90mm Width) Exposed Pad
- Datasheet:
-
ISL6506CBZ-T.pdf
- Description:
- IC PWR SUPPLY CTRLR/MONITR 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,013
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ISL6506CBZ-T from Renesas Electronics is a dual-rail ACPI-compliant linear power controller for motherboard 5VDUAL and 3.3VDUAL voltage regulation. It integrates an internal 3.3V LDO (2A current limit), 5VDUAL switch control, S3/S5 digital state interface, and thermal shutdown in an 8-lead EPSOIC package. Used in ATX-based microprocessor systems to manage USB/keyboard (5VDUAL) and PCI/LAN auxiliary (3.3VDUAL) rails during S0–S5 sleep states.
For engineers reviewing the ISL6506CBZ-T datasheet, ISL6506CBZ-T pinout, ISL6506CBZ-T application, or ISL6506CBZ-T equivalent, this page delivers verified functional identity, exact sleep-state behavior (5VDUAL active in S4/S5), confirmed 2A 3.3V LDO capability, thermal shutdown threshold (140°C), and validated alternative part selection for ACPI power sequencing designs.
Technical Context
The ISL6506CBZ-T implements dual-output ACPI state control via dedicated S3 and S5 digital inputs with internal 10µA pull-downs. Its architecture separates sleep-mode operation-using an integrated 3.3V LDO powered from 5VSB-and active-mode operation-routing ATX 3.3V/5V through external NMOS/PMOS switches under DLA and 5VDLSB gate drive control.
It features a 6.55–9.85ms soft-start interval, 58µs S0→S3 transition delay, and monitors both 5VSB (POR at 4.5V rising / 3.6–3.95V falling) and 12VATX (POR at 8.9–10.8V) to enforce safe power-up sequencing before entering S0. Undervoltage protection on 3.3VAUX triggers at 2.475V during sleep states only.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| 3.3VDUAL LDO Current Limit | 2A - supports high-current auxiliary loads like LAN PHY or PCIe slots in S3/S4/S5 sleep states |
| 5VDUAL State in S4/S5 | Active - maintains 5V supply to USB peripherals and keyboard/mouse even in deep sleep (S4/S5) |
| Thermal Shutdown Threshold | 140°C - protects against sustained overtemperature during high-load or poor heatsinking conditions |
| Soft-Start Interval | 6.55–9.85ms - controls inrush current during 3.3VDUAL and 5VDUAL rail ramp-up to prevent system reset |
| Supply Current (S0 State) | 3.60mA - ultra-low bias consumption enables efficient always-on auxiliary power management |
| 5VSB POR Threshold | 4.5V (rising), 3.6–3.95V (falling) - ensures reliable power-on reset and graceful shutdown under brownout |
| Package Type | 8-lead EPSOIC (M8.15C) - exposed pad enhances thermal dissipation for linear regulator operation |
Pinout & Package
8-lead Exposed Pad Small Outline Integrated Circuit (EPSOIC) package per drawing M8.15C; 1.422–1.700mm body height, 4.80–4.98mm width (D), 3.81–3.99mm length (E), EPAD thermally connected to GND via ≥3 vias.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pin 1) | Bias supply input | Connects to ATX 5VSB; powers internal circuitry and serves as input to 3.3V LDO; monitored for POR |
| 3V3AUX (Pin 2) | 3.3VDUAL output node | Delivers regulated 3.3V in sleep states (via internal LDO); connects to ATX 3.3V in active states (via external NMOS) |
| S3 (Pin 3) | Digital sleep-state input | High = S0/S1/S2; Low = S3; internal 10µA pull-down ensures defined state when unasserted |
| S5 (Pin 4) | Digital sleep-state input | High = S0/S1/S2/S3; Low = S4/S5; blocks illegal S4/S5→S3 transitions |
| GND (Pins 5 & EPAD) | Signal and thermal ground | Reference for all voltages; EPAD must be soldered to PCB ground plane for thermal performance |
| DLA (Pin 6) | Open-drain 12V gate driver | Pulls gates of external N-MOSFETs (Q1/Q3) to 12VATX in active state; used for 12V POR monitoring |
| 5VDLSB (Pin 7) | P-MOSFET gate driver | Drives gate of external P-MOSFET (Q2) to connect 5VSB to 5VDUAL in S3/S4/S5 sleep states |
| N/C (Pin 8) | No-connect | Not internally bonded; must remain unconnected per datasheet |
Key Features
| Feature | Design Value |
|---|---|
| ACPI S0–S5 Dual-Rail Control | Hardware-enforced state machine with S3/S5 inputs eliminates software dependency for compliant sleep/wake sequencing |
| Integrated 3.3V LDO (2A) | Eliminates need for external low-dropout regulator in S3/S4/S5, reducing BOM count and board area |
| 5VDUAL Active in S4/S5 | Enables wake-on-LAN, USB resume, and keyboard wake functionality without requiring full system power restoration |
| Thermal Shutdown + UVLO | 140°C junction shutdown and 2.475V 3.3VAUX undervoltage lockout prevent damage and ensure stable auxiliary rail operation |
| Programmable Soft-Start | Adjustable 5VDUAL ramp via external capacitor on Q2 gate-drain; prevents output overshoot and MOSFET stress |
Applications
| Desktop Motherboard Power Sequencing | Embedded ATX-Compatible Systems |
|---|---|
Use Scenario: Managing 5VDUAL and 3.3VDUAL rails on x86-based desktop motherboards compliant with ACPI 2.0+ specifications. IC Role / Device Role / Timing Role: Dual-rail power controller coordinating ATX 5V/3.3V/5VSB/12V inputs to generate S0–S5 state-aware outputs with hardware-enforced timing. Use Value: Enables zero-software wake-from-S5 via USB or LAN while maintaining strict ±2% 3.3VDUAL regulation across temperature. |
Use Scenario: Power management in industrial PC-104 or COM Express modules requiring legacy ATX compatibility and deep-sleep retention. IC Role / Device Role / Timing Role: Standby power supervisor delivering always-on 5VDUAL and regulated 3.3VDUAL during S4/S5 for remote management controllers (IPMI/BMC). Use Value: 2A 3.3V LDO sustains Ethernet PHY and flash memory I/O during extended S5, eliminating need for secondary regulators. |
| USB Peripheral Hub Power Control | Legacy BIOS-Compatible Wake Logic |
Use Scenario: Providing isolated, sequenced 5VDUAL to USB 2.0 hub ICs on add-in cards or daughterboards. IC Role / Device Role / Timing Role: Dedicated 5V rail controller ensuring clean power delivery during hot-plug events and S3→S0 transitions. Use Value: 58µs S0→S3 delay and soft-start prevent bus reset glitches; 5VDUAL remains live in S4/S5 for device enumeration on resume. |
Use Scenario: Enabling legacy BIOS wake sources (PS/2 keyboard, parallel port) in modern UEFI firmware environments. IC Role / Device Role / Timing Role: Hardware-level S3/S5 state translator converting SLP_S3/SLP_S5 signals into precise 3.3V/5V enable timing per ACPI spec. Use Value: Eliminates firmware patching for wake-source compatibility; guarantees 5VDUAL availability for PS/2 controller power during S5. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-rail ACPI power controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6506ACBZ-T | Same package and pinout; 1A 3.3V LDO instead of 2A; 5VDUAL remains active in S4/S5 | Lower 3.3VDUAL current capacity limits use in high-power auxiliary circuits (e.g., multi-port LAN) | Select ISL6506ACBZ-T only if total 3.3VDUAL load ≤1A and S4/S5 5VDUAL retention is required |
| ISL6506BCBZ-T | Same package and pinout; 2A 3.3V LDO; 5VDUAL shuts down in S4/S5 (vs. active in ISL6506CBZ-T) | Cannot support wake-on-LAN or USB resume from S4/S5 due to 5VDUAL removal | Choose ISL6506BCBZ-T only for cost-sensitive designs where S4/S5 wake capability is unnecessary |
Compared with ISL6506CBZ-T, ISL6506ACBZ-T trades 1A LDO current for identical S4/S5 5VDUAL retention, while ISL6506BCBZ-T offers same 2A LDO but removes 5VDUAL in deep sleep-making ISL6506CBZ-T the sole option balancing high-current auxiliary support with full ACPI wake functionality.
Availability
ISL6506CBZ-T is available at Aetrix Electronics and suitable for desktop motherboard design, embedded ATX-compatible systems, and USB peripheral power management requiring stable component supply across long-lifecycle production runs.
Supply support for ISL6506CBZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power management, and timing solutions for industrial, automotive, and computing markets.
The ISL6506 series belongs to Renesas' ACPI-compliant power controller product line, designed specifically to simplify motherboard-level power sequencing and reduce external component count in x86-compatible systems.
FAQ
What is the key functional difference between ISL6506CBZ-T and ISL6506BCBZ-T?
The ISL6506CBZ-T maintains 5VDUAL output during S4/S5 sleep states, enabling wake-on-LAN and USB resume, whereas ISL6506BCBZ-T shuts down 5VDUAL in S4/S5. Both share identical 2A 3.3VDUAL LDO capability and 8-lead EPSOIC packaging. The ISL6506CBZ-T is functionally equivalent to ISL6506ACBZ-T in S4/S5 behavior but provides higher 3.3V current capacity.
Does ISL6506CBZ-T require external MOSFETs, and if so, what types?
Yes, ISL6506CBZ-T requires three external MOSFETs: two N-channel devices (Q1, Q3) to connect ATX 3.3V and 5V to 3.3VDUAL and 5VDUAL in active states, and one P-channel device (Q2) to connect 5VSB to 5VDUAL in S3/S4/S5 sleep states. Q2 must be a logic-level P-MOSFET rated for ≤4.5V VGS turn-on.
What is the purpose of the DLA pin on ISL6506CBZ-T, and how is it used?
The DLA pin on ISL6506CBZ-T is an open-drain output that drives the gates of external N-MOSFETs (Q1 and Q3) using the ATX 12V rail. A mandatory 1kΩ pull-up resistor connects DLA to 12VATX. This configuration enables fast, low-loss switching of ATX 3.3V/5V into the auxiliary rails during S0 entry and also serves as the 12V power-on reset (POR) monitor input.
How does ISL6506CBZ-T handle undervoltage on the 3.3VDUAL rail?
The ISL6506CBZ-T monitors 3.3VDUAL (at the 3V3AUX pin) for undervoltage only during sleep states and after initial soft-start. If voltage drops below 2.475V (25% below nominal), the internal LDO disables, retries once after a soft-start interval, and permanently latches off after three failed retries-requiring a full 5VSB power cycle (POR) to reset.
Is ISL6506CBZ-T RoHS compliant and lead-free?
Yes, ISL6506CBZ-T is RoHS compliant and Pb-free, featuring 100% matte tin (e3) termination finish compatible with both SnPb and Pb-free soldering processes. It meets IPC/JEDEC J-STD-020 reflow profiles and is classified per Moisture Sensitivity Level (MSL) requirements specified in Renesas TB363.
ISL6506CBZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Applications:
- Power Supply Controller/Monitor
- Voltage - Input:
- -
- Voltage - Supply:
- 4.75V ~ 5.25V
- Current - Supply:
- 3.6 mA
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC-EP
ISL6506CBZ-T FAQ
1.How can I place an order for ISL6506CBZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6506CBZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6506CBZ-T reliable?
The price and inventory of ISL6506CBZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6506CBZ-T is usually 5 days.
3.What payment methods are accepted for ISL6506CBZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6506CBZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6506CBZ-T?
ISL6506CBZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6506CBZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6506CBZ-T?
For technical support, including ISL6506CBZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6506CBZ-T requirements.
6.How does Aetrix verify that ISL6506CBZ-T is sourced from the original manufacturer or authorized distributors?
All ISL6506CBZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6506CBZ-T meets industry standards.
7.What is the process for return or replacement of ISL6506CBZ-T?
All ISL6506CBZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL6506CBZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6506CBZ-T part is unused and in its original packaging.
Return procedure for ISL6506CBZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ISL6506CBZ-T Tags

-
UC3845AD8TR
Texas Instruments

-
UC2843AD8TR
Texas Instruments

-
LM3880MFX-1AE/NOPB
Texas Instruments

-
LM3880MFX-1AA/NOPB
Texas Instruments

-
INA234AIYBJR
Texas Instruments

-
INA700AYWFR
Texas Instruments

-
LM3880MF-1AE/NOPB
Texas Instruments

-
LM3880MF-1AA/NOPB
Texas Instruments

-
LM3881MM/NOPB
Texas Instruments

-
UCC2802DTR
Texas Instruments

-
NCP4305DMTTWG
onsemi
-
INA237AIDGSR
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

