My Inquiry
My Account
Renesas ISL6523CB
- Part No.:
- ISL6523CB
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
ISL6523CB.pdf
- Description:
- IC REG CTRLR VRM8.5 4OUT 28SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,516
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ISL6523CB from Intersil is a VRM8.5-compliant dual PWM and dual linear power system controller in 28-pin SOIC, delivering four regulated outputs: microprocessor core (1.05–1.825V, ±1%), AGTL+ bus (1.2V ±3%), AGP bus (1.5V ±3%), and chipset core (1.8V ±3%). It integrates voltage-mode PWM control, TTL-compatible 5-bit DAC, rDS(ON)-based overcurrent sensing, and sequenced soft-start for motherboard power delivery.
For engineers reviewing the ISL6523CB datasheet, ISL6523CB pinout, ISL6523CB application, or ISL6523CB equivalent, this page provides verified technical context, exact pin functions, real-world sequencing behavior, confirmed VRM8.5 DAC mapping, and validated alternative options for legacy PC power design continuity.
Technical Context
The ISL6523CB implements two independent voltage-mode PWM controllers: PWM1 (synchronous buck, core voltage) uses DACOUT-referenced error amplification with ±1% static regulation and 200kHz fixed-frequency operation; PWM2 (standard buck, AGTL+ 1.2V) employs separate feedback with ±3% tolerance and shared oscillator timing. Both use internal 200μA current sources and external ROCSET resistors to set overcurrent thresholds via upper MOSFET rDS(ON) sensing-eliminating current-sense resistors.
Two linear regulators (VOUT3 = 1.5V, VOUT4 = 1.8V) are driven by dedicated N-channel MOSFET/bipolar-compatible DRIVE3/DRIVE4 outputs, with under-voltage monitoring on VSEN3/VSEN4 and independent soft-start clamping via SS13/SS24 pins. Power sequencing is hardware-controlled: VTTPG asserts after SS24 reaches 1.25V, then PGOOD activates only when VOUT1 is within ±10% of DACOUT and all other outputs exceed their UV thresholds.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Supply Voltage | +12V ±10% - powers gate drivers, internal logic, and POR monitoring; absolute max +15V |
| PWM1 Output Range | 1.050V to 1.825V in 25mV steps - VRM8.5-compliant DAC programming via VID3–VID25 pins |
| PWM2 Output | 1.2V ±3% - fixed AGTL+ bus voltage with independent feedback loop and VTTPG open-collector status |
| Linear Outputs | VOUT3 = 1.5V ±3%, VOUT4 = 1.8V ±3% - externally driven by DRIVE3/DRIVE4 with VSEN3/VSEN4 UV detection |
| Oscillator Frequency | 185–215kHz (typ 200kHz) - constant-frequency operation enables predictable EMI filtering and inductor sizing |
| Overcurrent Sensing | rDS(ON)-based - no external sense resistor required; trip level set by ROCSET × IOCSET (200μA) |
| Soft-Start Control | SS13 (28μA source) controls VOUT1/VOUT3 ramp; SS24 (28μA source) controls VOUT2 ramp and VTTPG delay |
Pinout & Package
ISL6523CB is housed in a 28-lead SOIC package (M28.3 drawing), with exposed pad not specified and thermal resistance θJA = 70°C/W. Pin functions are validated per FN9024 Rev 2.00 datasheet Figures 1–3 and Functional Pin Descriptions (pp.5–6).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (28) | Bias supply input | +12V ±10% main IC supply; powers gate drivers and enables POR monitoring at 10.4V rising threshold |
| GND (17) | Signal reference | Common reference for all analog/digital circuits; separate from PGND to isolate noise-sensitive nodes |
| PGND (24) | Power ground return | Direct connection point for synchronous buck lower MOSFET source; minimizes high-di/dt ground bounce |
| UGATE1 (27), UGATE2 (1) | Upper MOSFET gate drive | 1A source capability; drives Q1/Q3 gates in synchronous/standard buck topologies |
| LGATE1 (25) | Lower MOSFET gate drive | 1A source/1.4Ω sink; enables synchronous rectification for VOUT1 with precise dead-time control |
| PHASE1 (26), PHASE2 (2) | Switch node sensing | Return path for gate drive current; used to measure rDS(ON) voltage drop for OC protection |
| VID3–VID0, VID25 (3–7) | DAC digital inputs | TTL-compatible 5-bit interface; internally pulled up to VAUX (3.3V) via 5kΩ resistors; defines core voltage per Table 1 |
| VSEN1 (22) | Core output feedback | Connects to VOUT1; sets PGOOD (±10% window) and OVP (115% DACOUT) thresholds |
| DRIVE3 (18), DRIVE4 (15) | Linear regulator pass element drive | 40mA sink/source; compatible with N-MOSFET or NPN bipolar transistors for VOUT3/VOUT4 |
| SS13 (13), SS24 (12) | Soft-start timing control | 28μA internal current source charges external capacitor; SS13 enables VOUT1/VOUT3; SS24 enables VOUT2/VTTPG |
Key Features
| Feature | Design Value |
|---|---|
| Four-output integration | Single-chip solution for Intel VRM8.5 core, AGTL+ 1.2V, AGP 1.5V, and chipset 1.8V rails-reduces BOM count and layout complexity |
| VRM8.5 DAC compliance | 5-bit TTL interface (VID3–VID25) with 25mV steps across 1.05–1.825V range; matches Intel microprocessor VID protocols |
| rDS(ON) overcurrent sensing | Eliminates discrete current-sense resistors for both PWM channels; reduces power loss and PCB area while maintaining accuracy |
| Hardware-sequenced power-up | VTTPG asserts before VOUT1 ramp begins; PGOOD only activates after all four outputs meet UV/OVP criteria-ensures safe CPU boot |
| Independent linear regulator control | DRIVE3/DRIVE4 outputs support MOSFET or bipolar pass devices; VSEN3/VSEN4 UV detection prevents latch-off during startup |
Applications
| Desktop Motherboard Core Regulation | AGTL+ Bus Power Delivery |
|---|---|
Use Scenario: Regulating Intel Pentium III/Xeon core voltage on ATX-compliant desktop motherboards with 3.3V/5V/12V ATX inputs. IC Role / Device Role / Timing Role: Primary VRM8.5 controller managing synchronous buck conversion, DAC-based voltage selection, and coordinated soft-start sequencing. Use Value: Enables precise ±1% core voltage regulation across temperature, supports dynamic VID changes, and guarantees safe power-on sequence per Intel specification. |
Use Scenario: Providing stable 1.2V ±3% AGTL+ termination voltage for front-side bus signaling on server/workstation motherboards. IC Role / Device Role / Timing Role: Secondary PWM controller with dedicated VTTPG open-collector status signal and independent feedback loop. Use Value: Delivers low-noise, tightly regulated bus voltage with early power-good indication (VTTPG) to enable memory controller initialization before CPU core ramp. |
| AGP Graphics Port Power | Chipset North/South Bridge Core |
Use Scenario: Supplying 1.5V ±3% power to AGP 4x graphics cards requiring strict voltage tolerance and fast transient response. IC Role / Device Role / Timing Role: Linear regulator channel driven by DRIVE3 with VSEN3-based under-voltage monitoring and SS13-synchronized ramp. Use Value: Eliminates need for separate LDO; supports rapid load steps via external N-MOSFET while maintaining <3% regulation error. |
Use Scenario: Powering 1.8V ±3% core logic of Intel 8xx/9xx series chipsets where tight voltage tracking relative to ATX 3.3V is mandatory. IC Role / Device Role / Timing Role: Linear regulator channel driven by DRIVE4 with independent soft-start clamping and VAUX-referenced bias. Use Value: Ensures VOUT4 never lags ATX 3.3V by >2V-meeting chipset spec requirements without external sequencing ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail VRM power controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6522CB | Single PWM + dual linear controller; lacks second PWM channel and VRM8.5 DAC; supports only 1.5V/1.8V linear outputs | Cannot regulate AGTL+ 1.2V bus or provide full VRM8.5 core voltage programming; suitable only for simpler 3-rail systems | Select ISL6522CB only if AGTL+ rail is omitted and core voltage is fixed or controlled externally. |
| RT8802AZSP | Three PWM + one linear controller; supports VRM9.0/10.x DAC; higher switching frequency (300kHz); no rDS(ON) OC sensing | Designed for newer Pentium 4/Core platforms; requires current-sense resistors; incompatible VID pin mapping and sequencing logic | Choose RT8802AZSP for VRM9.0+ designs needing higher frequency or triple PWM, but expect layout and firmware rework. |
Compared with ISL6523CB, ISL6522CB omits AGTL+ regulation and VRM8.5 DAC functionality-limiting it to non-AGTL+ legacy boards-while RT8802AZSP targets post-VRM8.5 platforms with different DAC architecture, higher frequency, and resistor-based current sensing, making direct substitution impractical without system-level redesign.
Availability
ISL6523CB is available at Aetrix Electronics and suitable for desktop motherboard power regulation, AGTL+ bus delivery, AGP graphics port supply, and chipset core voltage generation requiring stable component supply and long-term industrial availability.
Supply support for ISL6523CB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) is a U.S.-based analog and power management IC designer known for high-performance voltage regulators, PWM controllers, and precision analog solutions.
The ISL6523CB belongs to Intersil's VRM-compliant power system controller product line, engineered specifically for Intel-based PC motherboard power delivery with integrated sequencing, DAC-based core voltage control, and multi-rail regulation in compact SOIC packaging.
FAQ
What is the core voltage range supported by the ISL6523CB?
The ISL6523CB supports a microprocessor core voltage range of 1.050V to 1.825V in precise 25mV increments via its VRM8.5-compliant 5-bit DAC. This range is programmed using the VID3–VID25 input pins and is validated across temperature with ±1% static regulation accuracy. The DACOUT reference directly sets both the target output and associated overvoltage protection threshold (115% of DACOUT) for the ISL6523CB's primary PWM channel.
Does the ISL6523CB require external current-sense resistors for overcurrent protection?
No, the ISL6523CB does not require external current-sense resistors. It implements rDS(ON)-based overcurrent detection for both PWM channels using the voltage drop across the upper MOSFET's on-resistance. An internal 200μA current source (IOCSET) flows through an external ROCSET resistor to generate a reference voltage (VSET), which is compared against the MOSFET's VDS(ON). This method eliminates sense resistor losses and saves PCB space in the ISL6523CB design.
How does the ISL6523CB handle power sequencing between its four outputs?
The ISL6523CB enforces strict hardware-based sequencing: VTTPG (AGTL+ power-good) asserts first after SS24 reaches 1.25V; only then does the core PWM (VOUT1) begin ramping via SS13. PGOOD goes high only when VOUT1 is within ±10% of DACOUT *and* all other outputs exceed their under-voltage thresholds. This ensures safe CPU initialization and prevents race conditions in the ISL6523CB-powered system.
Can the ISL6523CB drive both MOSFETs and bipolar transistors in its linear regulator channels?
Yes, the ISL6523CB's DRIVE3 and DRIVE4 outputs are explicitly designed to drive either N-channel MOSFETs or NPN bipolar transistors for the 1.5V (VOUT3) and 1.8V (VOUT4) linear regulators. Each output provides 20–40mA sink/source capability and interfaces directly with the pass device's gate/base. The datasheet confirms compatibility with both technologies, enabling flexible implementation in the ISL6523CB's linear regulation stages.
What is the function of the SS13 and SS24 pins on the ISL6523CB?
SS13 and SS24 are soft-start timing pins on the ISL6523CB, each sourcing a precise 28μA internal current to charge external capacitors. SS24 controls the ramp-up of the AGTL+ 1.2V output (VOUT2) and delays VTTPG assertion; SS13 controls the ramp-up of the core voltage (VOUT1) and AGP 1.5V output (VOUT3). Their independent control enables compliant power sequencing and limits inrush current during startup in the ISL6523CB application.
ISL6523CB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VRM8.5
- Voltage - Input:
- 5V ~ 15V
- Number of Outputs:
- 4
- Voltage - Output:
- Multiple
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
ISL6523CB FAQ
1.How can I place an order for ISL6523CB through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6523CB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6523CB reliable?
The price and inventory of ISL6523CB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6523CB is usually 5 days.
3.What payment methods are accepted for ISL6523CB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6523CB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6523CB?
ISL6523CB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6523CB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6523CB?
For technical support, including ISL6523CB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6523CB requirements.
6.How does Aetrix verify that ISL6523CB is sourced from the original manufacturer or authorized distributors?
All ISL6523CB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6523CB meets industry standards.
7.What is the process for return or replacement of ISL6523CB?
All ISL6523CB units undergo pre-shipment inspection (PSI). If there is an issue with ISL6523CB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6523CB part is unused and in its original packaging.
Return procedure for ISL6523CB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ISL6523CB Tags
-
TPS51206DSQR
Texas Instruments
-
TPS51200DRCR
Texas Instruments
-
TPS51200DRCT
Texas Instruments
-
TPS62740DSSR
Texas Instruments
-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi
-
RT9026GSP
Richtek USA Inc.
-
LP2998MRX/NOPB
Texas Instruments
-
TPS51200QDRCRQ1
Texas Instruments
-
DPA423GN-TL
Power Integrations
-
LM10011SD/NOPB
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
