My Inquiry
My Account
Renesas ISL6524CBZ
- Part No.:
- ISL6524CBZ
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
ISL6524CBZ.pdf
- Description:
- IC REG CTRLR PWM 4OUT 28SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:4,872
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ISL6524CBZ from Renesas Electronics (formerly Intersil) is a VRM8.5-compliant quad-output power system controller integrating one voltage-mode PWM controller for microprocessor core voltage and three linear controllers for AGTL+ 1.2V, AGP 1.5V, and chipset core 1.8V rails. It features a 5-bit TTL DAC (1.050V–1.825V in 25mV steps), ±1% core regulation, ±3% linear output tolerance, 200kHz fixed-frequency oscillator, and MOSFET rDS(ON)-based overcurrent sensing - deployed in ATX motherboard power delivery.
For engineers reviewing the ISL6524CBZ datasheet, ISL6524CBZ pinout, ISL6524CBZ application, or ISL6524CBZ equivalent, key selection criteria include VRM8.5 DAC compatibility, integrated triple-linear + single-PWM architecture, SOIC-28 package footprint, soft-start sequencing control (SS13/SS24), and fault logic with latchable OVP/UV protection across all four outputs.
Technical Context
The ISL6524CBZ implements a single-loop voltage-mode PWM control architecture with high-bandwidth error amplifier (88dB DC gain, 15MHz GBWP) and full 0–100% duty cycle capability. Its internal 200kHz oscillator supports frequency adjustment via external RT resistor (185–215kHz range), while the VID3–VID25 5-bit DAC directly sets both the PWM reference (DACOUT) and associated PGOOD/OVP thresholds.
Three independent linear regulators use external N-channel MOSFETs or NPN transistors driven by DRIVE2/DRIVE3/DRIVE4 pins; output voltages are fixed at 1.2V (VSEN2), 1.5V (VSEN3 with FIX open), and 1.8V (VSEN4 with FIX open), each with ±3% regulation and dedicated undervoltage monitoring. Fault response includes counter-based restart on OC/UV events and latched shutdown on VOUT1 overvoltage or VOUT4 undervoltage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Supply | +12V ±10% bias input; powers gate drivers and internal circuitry |
| PWM Output Range | 1.050V to 1.825V in 25mV steps via VRM8.5-compatible 5-bit DAC |
| Core Regulation | ±1% static accuracy over temperature; enables tight CPU core voltage compliance |
| Linear Outputs | 1.2V ±3% (VOUT2), 1.5V ±3% (VOUT3), 1.8V ±3% (VOUT4); fixed or adjustable via FIX pin |
| Oscillator Frequency | 200kHz nominal (185–215kHz); programmable with external RT resistor |
| Overcurrent Sensing | Uses upper MOSFET rDS(ON); eliminates current-sense resistor in buck stage |
| Package | 28-pin SOIC (M28.3); RoHS-compliant Pb-free termination |
Pinout & Package
ISL6524CBZ is housed in a 28-lead SOIC package (M28.3), thermally rated for 0°C to 70°C ambient operation with θJA = 70°C/W. Pin functions are validated per FN9015 Rev 3.00 datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DRIVE2 (1) | Linear regulator gate/base driver | Drives N-MOSFET or NPN for 1.2V AGTL+ bus (VOUT2) |
| FIX (2) | Linear regulator voltage select | Grounding enables adjustable 1.5V/1.8V outputs; open configures fixed 1.5V/1.8V |
| VID3–VID0, VID25 (3–7) | DAC digital inputs | TTL-compatible 5-bit interface setting core voltage reference (DACOUT) |
| FAULT/RT (10) | Oscillator control / fault reporting | Resistor-to-GND sets switching frequency; pulled to VCC during OVP/OC fault |
| VSEN2 (11), VSEN3 (19), VSEN4 (14) | Linear regulator feedback | Monitor 1.2V, 1.5V, and 1.8V outputs for regulation and undervoltage detection |
| SS13 (13), SS24 (12) | Soft-start timing control | Capacitor-connected nodes controlling ramp-up sequence of PWM and linear outputs |
| VTTPG (9), PGOOD (8) | Power-good status outputs | Open-collector signals indicating VOUT2 readiness and full-system power-good status |
| UGATE (27), LGATE (25) | PWM gate drivers | Drive upper/lower N-MOSFETs in synchronous buck converter for core voltage |
Key Features
| Feature | Design Value |
|---|---|
| Quad-output integration | Single IC delivers regulated core (PWM), AGTL+ (1.2V), AGP (1.5V), and chipset (1.8V) rails - reduces BOM count and layout complexity |
| VRM8.5 DAC compliance | 5-bit TTL interface (VID3–VID25) with 25mV step resolution enables direct compatibility with Intel Pentium III/IV-era CPUs |
| rDS(ON)-based current sensing | Eliminates discrete current-sense resistor in buck stage, improving efficiency and reducing thermal stress |
| Sequenced soft-start | Independent SS13/SS24 timing controls ensure VOUT4 (1.8V) ramps before VOUT2 (1.2V), meeting ATX 3.3V–1.8V <2V differential requirement |
| Dual power-good signaling | VTTPG asserts early for AGTL+ bus readiness; PGOOD asserts only after all four outputs meet regulation and UV thresholds |
Applications
| Desktop Motherboard Power | AGP Graphics Power Delivery |
|---|---|
Use Scenario: Regulating core voltage for Intel Pentium III/IV processors and auxiliary rails on ATX desktop motherboards. IC Role / Device Role / Timing Role: Primary power system controller managing synchronized startup, dynamic voltage scaling via VID, and fault-safe shutdown. Use Value: Enables precise ±1% core regulation and compliant VRM8.5 sequencing without external DAC or discrete linear controllers. | Use Scenario: Providing stable 1.5V power to AGP 4x graphics cards requiring strict voltage tolerance and fast transient response. IC Role / Device Role / Timing Role: Linear regulator controller (EA3 + DRIVE3) with dedicated VSEN3 feedback and UV monitoring. Use Value: Delivers ±3% 1.5V output with built-in undervoltage lockout, eliminating need for external supervisor IC on AGP rail. |
| Chipset Core Voltage Supply | AGTL+ Bus Regulation |
Use Scenario: Generating 1.8V for northbridge/southbridge core logic in legacy PC chipsets. IC Role / Device Role / Timing Role: Linear regulator controller (EA4 + DRIVE4) with independent soft-start (SS24) and VSEN4 monitoring. Use Value: Ensures VOUT4 ramps within 2V of ATX 3.3V supply, satisfying chipset power sequencing requirements. | Use Scenario: Supplying 1.2V AGTL+ signaling voltage for CPU-to-chipset communication buses. IC Role / Device Role / Timing Role: Linear regulator controller (EA2 + DRIVE2) with delayed VTTPG assertion and VSEN2 UV detection. Use Value: Provides early power-good indication (VTTPG) to enable downstream logic before full system PGOOD assertion. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output VRM power controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6522CBZ | VRM8.4-compliant; 4-bit VID (1.10V–1.85V, 50mV steps); no FIX pin for linear output adjustment | Limited to older Pentium II/early Pentium III CPUs; lacks 1.2V AGTL+ support and flexible linear configuration | Select only for legacy VRM8.4 designs where 25mV DAC resolution and AGTL+ 1.2V are not required. |
| RT9238GQW | VRM9.0-compliant; 6-bit VID (0.725V–1.85V, 25mV steps); integrated MOSFET drivers; no linear regulator channels | Targets Pentium 4 and later CPUs; requires external linear regulators for auxiliary rails | Choose when upgrading to VRM9.0 and using discrete linear stages; not suitable as drop-in replacement for ISL6524CBZ's integrated linear function. |
Compared with ISL6522CBZ and RT9238GQW, the ISL6524CBZ uniquely combines VRM8.5 DAC precision, integrated triple-linear regulation, and sequenced soft-start in a single SOIC-28 package - making it irreplaceable in ATX motherboards requiring native AGTL+ 1.2V, AGP 1.5V, and chipset 1.8V support without external linear controllers.
Availability
ISL6524CBZ is available at Aetrix Electronics and suitable for desktop motherboard design, AGP graphics power subsystems, and legacy chipset power delivery requiring stable component supply and long-term industrial availability.
Supply support for ISL6524CBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics acquired Intersil in 2017 and maintains full support for its legacy power management portfolio, including VRM controllers.
The ISL6524CBZ belongs to Intersil's VRM8.x power system controller product line, designed specifically for Intel-compatible desktop motherboard power delivery with integrated multi-rail regulation and Intel-specification DAC compliance.
FAQ
What is the operating temperature range for the ISL6524CBZ?
The ISL6524CBZ is specified for an ambient operating temperature range of 0°C to 70°C, with a maximum junction temperature of 125°C. Its SOIC-28 package has a thermal resistance θJA of 70°C/W under standard test conditions. This rating aligns with commercial-grade motherboard environments and is confirmed in the Absolute Maximum Ratings table of the FN9015 datasheet. The ISL6524CBZ must be used within these limits to maintain ±1% core regulation and reliable fault protection behavior.
How does the ISL6524CBZ implement overcurrent protection without a sense resistor?
The ISL6524CBZ uses the upper MOSFET's rDS(ON) as the current-sensing element in the synchronous buck stage. An internal 200µA current source (IOCSET) develops a voltage across an external ROCSET resistor, which sets the overcurrent trip threshold. When the voltage drop across the upper MOSFET (iD × rDS(ON)) exceeds this reference, the OC comparator triggers. This method eliminates the need for a discrete current-sense resistor, reducing power loss and board space - a key feature documented in the Functional Pin Descriptions and Overcurrent Protection sections of the ISL6524CBZ datasheet.
Can the ISL6524CBZ support adjustable linear output voltages?
Yes - the ISL6524CBZ supports adjustable 1.5V and 1.8V linear outputs via the FIX pin. When FIX is grounded, internal resistor dividers are bypassed, allowing external resistor networks on VSEN3 or VSEN4 to set output voltages from 1.26V up to the input supply (e.g., +3.3V or +5V). The formula VOUT = 1.265V × (1 + ROUT/RGND) applies. This adjustability is explicitly defined in the Functional Pin Descriptions section of the ISL6524CBZ datasheet and enables flexibility beyond the default fixed 1.5V/1.8V settings.
What is the purpose of the SS13 and SS24 pins on the ISL6524CBZ?
SS13 and SS24 are dedicated soft-start timing pins that control the ramp-up sequence of the ISL6524CBZ's outputs. SS13 governs the synchronous PWM (VOUT1) and AGP linear (VOUT3) regulators; SS24 controls the AGTL+ linear (VOUT2) regulator. Each connects to an external capacitor charged by an internal 28µA current source. Their independent timing ensures VOUT4 (1.8V chipset) ramps first, followed by VOUT2, then VOUT1/VOUT3 - satisfying ATX sequencing requirements. This dual-soft-start architecture is detailed in the Soft-Start section of the ISL6524CBZ datasheet.
Does the ISL6524CBZ provide separate power-good signals for different rails?
Yes - the ISL6524CBZ provides two distinct open-collector power-good signals: VTTPG (Pin 9) and PGOOD (Pin 8). VTTPG asserts high when VOUT2 (1.2V AGTL+) reaches 90% of its target and remains above undervoltage threshold, enabling early logic enablement. PGOOD asserts only after VOUT1 is within ±10% of its DAC-set value AND all other outputs exceed their respective undervoltage levels. This staged signaling is critical for proper ATX motherboard power sequencing and is fully specified in the Electrical Specifications and Functional Pin Descriptions of the ISL6524CBZ datasheet.
ISL6524CBZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VRM8.5
- Voltage - Input:
- 10.8V ~ 13.2V
- Number of Outputs:
- 4
- Voltage - Output:
- Multiple
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
ISL6524CBZ FAQ
1.How can I place an order for ISL6524CBZ through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6524CBZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6524CBZ reliable?
The price and inventory of ISL6524CBZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6524CBZ is usually 5 days.
3.What payment methods are accepted for ISL6524CBZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6524CBZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6524CBZ?
ISL6524CBZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6524CBZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6524CBZ?
For technical support, including ISL6524CBZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6524CBZ requirements.
6.How does Aetrix verify that ISL6524CBZ is sourced from the original manufacturer or authorized distributors?
All ISL6524CBZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6524CBZ meets industry standards.
7.What is the process for return or replacement of ISL6524CBZ?
All ISL6524CBZ units undergo pre-shipment inspection (PSI). If there is an issue with ISL6524CBZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6524CBZ part is unused and in its original packaging.
Return procedure for ISL6524CBZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ISL6524CBZ Tags
-
TPS51206DSQR
Texas Instruments
-
TPS51200DRCR
Texas Instruments
-
TPS51200DRCT
Texas Instruments
-
TPS62740DSSR
Texas Instruments
-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi
-
RT9026GSP
Richtek USA Inc.
-
LP2998MRX/NOPB
Texas Instruments
-
TPS51200QDRCRQ1
Texas Instruments
-
DPA423GN-TL
Power Integrations
-
LM10011SD/NOPB
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
