My Inquiry
My Account
Renesas ISL6566CRZAR5184
- Part No.:
- ISL6566CRZAR5184
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
ISL6566CRZAR5184.pdf
- Description:
- IC REG CTRLR INTEL 1OUT 40QFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,793
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ISL6566CRZAR5184 from Renesas (formerly Intersil) is a three-phase buck PWM controller with integrated high- and low-side MOSFET drivers, designed for precision core voltage regulation in Intel VRM9/VRM10 and AMD Hammer microprocessor power delivery systems. It supports 1–3-phase operation, delivers ±0.5% system accuracy over temperature, uses dual DCR/rDS(ON) current sensing for load-line droop and channel-current balance, and operates up to 1.5 MHz per phase.
For engineers reviewing the ISL6566CRZAR5184 datasheet, ISL6566CRZAR5184 pinout, ISL6566CRZAR5184 application, or ISL6566CRZAR5184 equivalent, key selection considerations include its integrated gate drivers (5–12 V bias), differential remote sensing (VDIFF), programmable VID decoding (6-bit DAC), lossless DCR-based load line, and rDS(ON)-based per-channel current balancing - all in a Pb-free 40-lead 6×6 mm QFN package.
Technical Context
The ISL6566CRZAR5184 implements interleaved three-phase PWM control with adaptive non-overlap timing (10 ns UGATE/LGATE turn-on delay) and a dedicated clock generator supporting up to 1.5 MHz per phase. Its error amplifier features 96 dB DC gain and 20 MHz gain-bandwidth product, enabling stable compensation across wide load transients.
Current sensing combines two independent paths: DCR-based sampling at ISUM/IREF/ICOMP for load-line voltage positioning and overcurrent protection, and rDS(ON)-based sampling at ISEN1–ISEN3 for real-time per-channel current balancing - both validated for simultaneous use in the same design.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating Temp Range | 0°C to +70°C ambient - suitable for commercial-grade server CPU VRMs and embedded compute modules. |
| Switching Frequency | Up to 1.5 MHz per phase - enables smaller magnetics and faster transient response in space-constrained applications. |
| System Accuracy | ±0.5% over temperature (VID = 1.0–1.85 V) - ensures tight core voltage regulation under thermal stress. |
| Gate Drive Bias Range | 5 V to 12 V - supports optimal RDS(ON) reduction in modern low-VGS MOSFETs without excessive shoot-through risk. |
| OCSET Trip Current | 100 µA ±7% - sets overcurrent threshold via single external resistor; enables precise, scalable current-limit tuning. |
| Droop Programming | Lossless DCR sensing at ISUM/IREF/ICOMP - eliminates sense-resistor power loss while enabling accurate load-line slope control. |
| VID Compatibility | 6-bit DAC supporting Intel VRM9.0, VRM10.0, and AMD Hammer codes - allows single-controller reuse across multiple CPU platforms. |
Pinout & Package
ISL6566CRZAR5184 is housed in a Pb-free, RoHS-compliant 40-lead 6×6 mm QFN package (PKG DWG # L40.6x6) with exposed thermal pad. The package supports reflow soldering per IPC/JEDEC J-STD-020 MSL level matching Pb-free peak temperatures.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VID0–VID4, VID12.5 | DAC input logic | Encode microprocessor core voltage setpoint; VID12.5 + VRM10 pin select Intel VRM9/VRM10 or AMD Hammer DAC mapping. |
| UGATE1–3, LGATE1–3 | MOSFET gate drivers | Drive upper/lower synchronous FETs per phase; integrated shoot-through protection with 10 ns adaptive non-overlap. |
| ISEN1–3 | rDS(ON) current sense input | Sample lower-FET conduction current for per-phase current balancing; requires external RISEN to PHASE node. |
| ISUM, IREF, ICOMP | DCR current sense interface | Implement lossless inductor DCR sensing for load-line droop and overcurrent protection; IREF connects to output sum point. |
| VDIFF | Differential remote-sense output | Sum of remote-sensed VOUT and DCR-derived droop voltage - used as error amplifier reference (FB). |
| ENLL | Enable input | 0.66 V threshold enable with 100 mV hysteresis; internal 1 µA pull-up to VCC - supports simple power-sequencing control. |
| PGOOD | Power-good indicator | Open-drain output asserted high only when VOUT is within ±5% UV/OV limits and soft-start complete. |
| FS | Frequency set | Resistor-to-ground sets switching frequency (e.g., 100 kΩ → 250 kHz); supports up to 1.5 MHz with external oscillator sync. |
Key Features
| Feature | Design Value |
|---|---|
| Dual current sensing | Simultaneous DCR (for droop/OCP) and rDS(ON) (for channel balance) sensing - eliminates trade-off between accuracy and efficiency in multi-phase VRMs. |
| Differential remote sensing | VDIFF output compensates for PCB IR drop between VRM and CPU VSS/VDD pins - maintains ±0.5% regulation at load point. |
| Dynamic VID support | Internal DAC updates reference during CPU state transitions (C-states, Turbo Boost) without external intervention - enables dynamic voltage scaling. |
| Programmable voltage offset | OFS pin sinks or sources 50 µA ±5% to generate positive/negative DC offset across FB–VDIFF resistor - fine-tunes load-line intercept. |
| Multi-tier overvoltage protection | Two-level OVP: clamping (lower FET ON) for fast transients, and shutdown for sustained overvoltage - protects CPU from catastrophic rail faults. |
Applications
| Server CPU Power Delivery | Workstation GPU Core VRM |
|---|---|
Use Scenario: Regulating 1.0–1.55 V core supply for dual-socket Xeon or EPYC processors under dynamic 30–120 A loads. IC Role / Device Role / Timing Role: Three-phase PWM controller with integrated drivers, DCR droop, and rDS(ON) current balancing - manages phase interleaving, load-line slope, and per-phase current matching. Use Value: Enables <1% output voltage deviation during 50 A/µs load steps while maintaining thermal balance across three discrete power stages. |
Use Scenario: Delivering tightly regulated 0.8–1.2 V to high-end discrete GPUs (e.g., AMD Radeon Instinct or NVIDIA A100) with aggressive DVFS requirements. IC Role / Device Role / Timing Role: VRM controller supporting AMD Hammer VID codes and dynamic offset adjustment - adapts output voltage during GPU clock/voltage scaling events. Use Value: Achieves ±0.5% system accuracy across -20°C to +70°C ambient, critical for GPU stability during sustained compute workloads. |
| Embedded AI Accelerator Module | High-Performance Computing Blade |
Use Scenario: Powering ASIC-based AI inference accelerators requiring 1.1–1.3 V at up to 60 A with minimal board area. IC Role / Device Role / Timing Role: Compact three-phase controller using 6×6 mm QFN package and lossless DCR sensing - replaces discrete controller+driver solutions. Use Value: Reduces component count by 12+ parts vs. legacy two-chip architecture, lowering BOM cost and improving layout density. |
Use Scenario: Multi-rail power system in 1U HPC blade where thermal management and transient response are constrained by airflow and chassis height. IC Role / Device Role / Timing Role: Interleaved three-phase controller with 1.5 MHz max switching and digital soft-start - minimizes output capacitor count and improves startup reliability. Use Value: Delivers 36 A load-step response <10 µs with <50 mV undershoot, meeting strict platform power integrity specs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar three-phase VRM controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IR35201MTRPBF | Supports up to 4 phases; includes PMBus interface and telemetry; no integrated gate drivers - requires external driver ICs. | Better suited for telemetry-enabled server platforms requiring real-time voltage/current/temp reporting. | Choose IR35201MTRPBF if PMBus monitoring and 4-phase scalability are required; avoid if gate-driver integration and minimal BOM are priorities. |
| TPS53679RSLR | Single-chip 3-phase controller with integrated drivers; supports CSD (Controlled Slew Rate) for EMI reduction; VID range limited to VRM10/11 only. | Optimized for Intel client/server CPUs with VRM10.1/11 compliance; lacks AMD Hammer VID support. | Choose TPS53679RSLR for Intel-centric designs needing enhanced EMI control; retain ISL6566CRZAR5184 for AMD compatibility or legacy VRM9 support. |
Compared with IR35201MTRPBF and TPS53679RSLR, the ISL6566CRZAR5184 uniquely combines native AMD Hammer VID decoding, dual DCR/rDS(ON) sensing, and integrated drivers in a commercial-temp QFN - making it optimal for cost-sensitive, multi-CPU-platform VRMs where telemetry and 4-phase expansion are unnecessary.
Availability
ISL6566CRZAR5184 is available at Aetrix Electronics and suitable for server CPU power delivery, workstation GPU core VRMs, embedded AI accelerator modules, and high-performance computing blades requiring stable component supply across long production lifecycles.
Supply support for ISL6566CRZAR5184 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics acquired Intersil in 2017 and maintains full technical and supply-chain continuity for the ISL6566 family. Renesas is a global leader in microcontrollers, analog, and power management ICs with broad industrial and computing market presence.
The ISL6566CRZAR5184 belongs to Renesas' high-performance VRM controller product line, engineered specifically for multi-phase core voltage regulation in x86 and x86-64 microprocessors - emphasizing precision, integration, and platform flexibility across Intel and AMD ecosystems.
FAQ
What is the operating temperature range for the ISL6566CRZAR5184?
The ISL6566CRZAR5184 is rated for 0°C to +70°C ambient operation, as confirmed in the FN9178 Rev 4.00 datasheet Section "Recommended Operating Conditions". This commercial-grade rating aligns with its target applications in server motherboards and embedded compute modules where airflow and thermal design ensure junction temperature remains below 150°C. The device's thermal resistance (θJA = 32°C/W) supports reliable operation under typical VRM power dissipation profiles.
Does the ISL6566CRZAR5184 support AMD Hammer microprocessors?
Yes, the ISL6566CRZAR5184 natively supports AMD Hammer VID codes via configuration of the VRM10 and VID12.5 pins: when VRM10 is low and VID12.5 is low, the internal 5-bit DAC decodes VID inputs per Table 2 in the FN9178 datasheet, enabling output voltages from 0.800 V to 1.550 V in 25 mV steps - matching AMD Hammer processor requirements.
How does the ISL6566CRZAR5184 implement current balancing across phases?
The ISL6566CRZAR5184 achieves per-phase current balancing using rDS(ON) current sensing at ISEN1–ISEN3 pins. During each lower-MOSFET conduction interval, an internal op-amp measures voltage across an external RISEN resistor connected to the PHASE node, generating a current proportional to channel load. This sampled current is compared to the cycle-average current (IAVG), and pulse-width correction is applied to minimize imbalance - a method detailed in Figure 3 and Section "Channel-Current Balance" of FN9178.
Can the ISL6566CRZAR5184 be configured for single-phase operation?
Yes, the ISL6566CRZAR5184 supports 1-, 2-, or 3-phase operation via PVCC pin configuration: for single-phase mode, both PVCC2 and PVCC3 must be left unconnected or grounded. This disables channels 2 and 3, causing PWM2 and PWM3 signals to remain inactive while PWM1 controls the sole active phase - as specified in the "PWM Operation" section (Page 11) of FN9178 Rev 4.00.
What package type and lead finish does the ISL6566CRZAR5184 use?
The ISL6566CRZAR5184 uses a 40-lead 6×6 mm QFN package (drawing L40.6x6) with Pb-free (RoHS-compliant) matte tin termination, as documented in the "Ordering Information" table on Page 2 of FN9178 Rev 4.00. The package includes an exposed thermal pad and is qualified for standard SnPb and Pb-free reflow processes per IPC/JEDEC J-STD-020.
ISL6566CRZAR5184 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VRM9, VRM10, AMD Hammer Applications
- Voltage - Input:
- 3V ~ 12V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.8V ~ 1.6V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-QFN (6x6)
ISL6566CRZAR5184 FAQ
1.How can I place an order for ISL6566CRZAR5184 through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL6566CRZAR5184 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL6566CRZAR5184 reliable?
The price and inventory of ISL6566CRZAR5184 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL6566CRZAR5184 is usually 5 days.
3.What payment methods are accepted for ISL6566CRZAR5184?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL6566CRZAR5184 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL6566CRZAR5184?
ISL6566CRZAR5184 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL6566CRZAR5184 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL6566CRZAR5184?
For technical support, including ISL6566CRZAR5184 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL6566CRZAR5184 requirements.
6.How does Aetrix verify that ISL6566CRZAR5184 is sourced from the original manufacturer or authorized distributors?
All ISL6566CRZAR5184 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL6566CRZAR5184 meets industry standards.
7.What is the process for return or replacement of ISL6566CRZAR5184?
All ISL6566CRZAR5184 units undergo pre-shipment inspection (PSI). If there is an issue with ISL6566CRZAR5184, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL6566CRZAR5184 part is unused and in its original packaging.
Return procedure for ISL6566CRZAR5184:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ISL6566CRZAR5184 Tags
-
TPS51206DSQR
Texas Instruments
-
TPS51200DRCR
Texas Instruments
-
TPS51200DRCT
Texas Instruments
-
TPS62740DSSR
Texas Instruments
-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi
-
RT9026GSP
Richtek USA Inc.
-
LP2998MRX/NOPB
Texas Instruments
-
TPS51200QDRCRQ1
Texas Instruments
-
DPA423GN-TL
Power Integrations
-
LM10011SD/NOPB
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
