Renesas ISL6568CR-T

Overview

ISL6568CR-T from Renesas (formerly Intersil) is a two-phase buck PWM controller with integrated high- and low-side MOSFET drivers, designed for precision core voltage regulation in Intel VRM9/VRM10 and AMD Hammer microprocessor power delivery systems. It supports 1–2-phase operation, delivers ±0.5% system accuracy over temperature, uses dual DCR/r_DS(ON) current sensing for load-line droop and channel-current balance, and operates up to 1.5 MHz per phase.

For engineers reviewing the ISL6568CR-T datasheet, ISL6568CR-T pinout, ISL6568CR-T application, or ISL6568CR-T equivalent, this page provides verified technical context on its multi-phase PWM architecture, remote differential sensing, VID decoding flexibility, gate drive bias range (5–12 V), and protection features including multi-tiered OVP/UVP/OCP - all critical for server CPU VRM, workstation power, and high-density embedded computing designs.

Technical Context

The ISL6568CR-T implements interleaved two-phase PWM control using an internal sawtooth oscillator with frequency set by an external resistor on FS (225–275 kHz typical at RT = 100 kΩ), supporting up to 1.5 MHz via design optimization. Its error amplifier features 96 dB DC gain and 20 MHz GBW, enabling stable loop response with external R-C compensation on FB/COMP/REF.

It integrates dual current-sensing paths: lossless inductor DCR sensing (via ISUM/IREF/ICOMP) for accurate load-line voltage positioning and overcurrent protection, and r_DS(ON)-based sensing (via ISEN1/ISEN2) for real-time per-channel current sampling and dynamic pulse-width correction to maintain ≤±3% channel-current imbalance across load range.

Key Specifications

Pinout & Package

ISL6568CR-T is housed in a 32-lead, 5 mm × 5 mm, 0.5 mm pitch QFN package (Pb-free, RoHS compliant) with exposed thermal pad. Pin functions are validated per FN9187 Rev 5.00 datasheet, Page 2 (Pin Configuration) and Page 8 (Functional Pin Description).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar two-phase buck controller applications.

Compared with ISL6568CR-T, ISL6566CRZ reduces phase count and feature set for simpler, lower-current applications, while RT8803AZSP extends phase count and current capability but abandons AMD compatibility and requires layout changes - neither offers pin-to-pin or functional equivalence without circuit modification.

Availability

ISL6568CR-T is available at Aetrix Electronics and suitable for server motherboard VRM design, workstation power subsystems, and AMD Hammer-compatible embedded computing platforms requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for ISL6568CR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation acquired Intersil in 2017 and maintains full product support, documentation, and manufacturing continuity for the ISL6568 family.

The ISL6568 belongs to Renesas' high-performance analog power management portfolio, engineered specifically for multi-phase CPU/GPU core voltage regulation in computing infrastructure where precision, thermal efficiency, and VID protocol flexibility are critical.

FAQ

What is the operating temperature range for the ISL6568CR-T?

The ISL6568CR-T is rated for 0°C to +70°C ambient operation, as specified in the ordering information table (FN9187 Rev 5.00, Page 2). This commercial-grade temperature range aligns with standard server motherboard and desktop computing environments. For extended industrial use, the ISL6568IRZ variant supports −40°C to +85°C and shares identical electrical specifications and pinout with the ISL6568CR-T.

How does the ISL6568CR-T implement current balancing between phases?

The ISL6568CR-T achieves channel-current balance using r_DS(ON) current sensing on ISEN1 and ISEN2 pins. During each lower-FET conduction interval, it samples the voltage drop across the MOSFET's on-resistance, generates a proportional current, and compares it to the average channel current (IAVG). The resulting error signal dynamically adjusts PWM pulse width per phase to maintain ≤±3% imbalance - confirmed in the "Channel-Current Balance" section (Page 11) and Electrical Specifications (Page 7, OCSET/ICOMP offset limits).

Can the ISL6568CR-T be configured for single-phase operation?

Yes - the ISL6568CR-T supports single-phase operation by connecting both BOOT2 and PHASE2 pins to +12 V, which disables the second channel and forces PWM2 inactive. This configuration retains full functionality of the first phase, including DCR current sensing, VID decoding, and protection features. The datasheet explicitly confirms this in the "PWM Operation" section (Page 10), noting that the default is two-phase but single-phase is selectable via pin strapping.

What is the purpose of the OFS pin on the ISL6568CR-T?

The OFS pin on the ISL6568CR-T sources or sinks a precision 50 µA ±2.5% current to generate a programmable DC offset voltage between FB and VDIFF. Connecting an external resistor from OFS to GND creates a negative offset; connecting to VCC creates a positive offset. This allows fine adjustment of the load-line droop slope without modifying the DCR sensing network - a key feature for optimizing transient response in high-performance CPU VRMs per FN9187 Section "OFS" (Page 9).

Does the ISL6568CR-T support AMD Hammer VID codes?

Yes - the ISL6568CR-T fully supports AMD Hammer VID codes via the VID12.5 pin. When VID12.5 is pulled to +5 V through a 5 kΩ resistor, the internal DAC decodes VID0–VID4 into the 25-step AMD voltage table ranging from 0.800 V to 1.550 V in 25 mV increments (Table 2, Page 12). This mode is explicitly documented in the DAC Select Table (Table 1) and verified in the "Output Voltage Setting" section (Page 12) of FN9187 Rev 5.00.