Renesas ISL68147IRAZ-T
- Part No.:
- ISL68147IRAZ-T
- Manufacturer:
- Renesas
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
ISL68147IRAZ-T.pdf
- Description:
- GP X+Y 7 PHASE DIGI CONT 48LD 6X
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL68147IRAZ-T from Renesas (formerly Intersil) is a digital dual-output, 7-phase configurable PWM controller designed for Cavium Thunder X2 server-class processors. It supports flexible phase allocation (e.g., 6+1, 5+2, 4+3), PMBus 1.3 telemetry, and linear synthetic digital current modulation for sub-100ns transient response. It delivers ±0.5% closed-loop system accuracy with differential remote sensing and enables high-efficiency point-of-load regulation in multi-rail server VRs.
For engineers reviewing the ISL68147IRAZ-T datasheet, ISL68147IRAZ-T pinout, ISL68147IRAZ-T application, or ISL68147IRAZ-T equivalent, key selection criteria include its 7-phase total capacity, dual-edge modulation architecture, auto phase add/drop thresholds, DCR/SPS current sensing compatibility, and support for up to 14-phase operation via ISL6617A phase doubler.
Technical Context
The ISL68147IRAZ-T implements a proprietary linear synthetic digital current modulation scheme with zero-latency synthetic current control and dual-edge PWM for fast transient response. Its digital core supports independent voltage loop tuning per output and programmable droop coefficients.
It integrates a full PMBus 1.3 interface with up to 2MHz SCL frequency, supporting real-time telemetry of VIN, VOUT, IOUT, temperature, power, and fault status registers. Fault management includes pulse-by-pulse phase OCP, total output current protection, OV/UV on input/output, open-sense detection, and black-box fault logging.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Configuration | X+Y ≤ 7 phases across two outputs (e.g., 6+1, 5+2, 4+3, 7+0); supports DCR, resistor, or smart power stage current sensing |
| Switching Frequency | 200–1000 kHz adjustable; ±4% accuracy at 500 kHz - enables optimization of efficiency vs. size in high-current VR designs |
| Voltage Accuracy | ±0.5% over load/line/temp for 0.8–3.05 V setpoints - ensures tight regulation for CPU/FPGA core rails |
| Current Sensing Accuracy | ±2% ISEN-to-ADC accuracy - critical for precise load-line control and cycle-by-cycle OCP threshold stability |
| PMBus Interface | PMBus 1.3 compliant; up to 2 MHz bus speed - enables high-bandwidth telemetry and dynamic configuration in server BMC environments |
| Thermal Monitoring | −50°C to +150°C range; ±4.5°C accuracy at TMON pins - supports diode-based or smart power stage thermal feedback for adaptive phase shedding |
| Supply Voltage | VCC = 3.3 V ±5%; VCCS = 1.25 V LDO output - requires local 4.7 µF MLCC decoupling for stable internal logic operation |
Pinout & Package
ISL68147IRAZ-T is housed in a RoHS-compliant 48-lead QFN package (6 mm × 6 mm, 0.5 mm pitch) with exposed thermal pad (EPAD) for enhanced thermal dissipation. The package supports reflow per IPC/JEDEC J-STD-020 MSL3 profile.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PWM[0:6] | PWM output drivers | Seven 3.3V logic-compatible outputs driving smart power stages or DrMOS; enable up to 7-phase per output or split configurations |
| CS[0:6], CSRTN[0:6] | Differential current sense inputs | Support DCR, resistor, or ISL99227 smart power stage sensing; unused phases must be grounded |
| VSEN0/RGND0, VSEN1/RGND1 | Differential remote voltage sense | Enable ±0.5% closed-loop accuracy; require Kelvin connections to load for precision regulation |
| EN0/EN1 | Output enable controls | Active-high logic inputs; tie to GND if unused; allow independent sequencing of dual outputs |
| PG0/PG1 | Open-drain power-good indicators | Signal valid regulation per output; require external pull-up to VCC (max 3.3 V) |
| SCL/SDA/SALRT | PMBus interface signals | Support SMBus 2.0/PMBus 1.3 communication; SALRT provides interrupt-on-fault capability |
| TMON0/TMON1 | External temperature monitor inputs | Accept diode-connected transistor or smart power stage thermal diode signals for per-rail thermal management |
| CONFIG, SA | Configuration ID and PMBus address select | Pin-strapped nonvolatile memory selection (up to 8 configs); SA sets unique SMBus address for multi-controller systems |
Key Features
| Feature | Design Value |
|---|---|
| Auto phase add/drop | User-programmable thresholds via PowerNavigator GUI - maintains peak efficiency across 0–100% load range without manual tuning |
| Dual-edge modulation | Enables fastest possible transient response by updating both leading and trailing edges each cycle - reduces output voltage deviation during load steps |
| Diode braking | Actively clamps overshoot during rapid load release - eliminates need for external snubbers in high-dV/dt server applications |
| On-chip NVM storage | Stores up to 8 complete configurations (voltage, phase count, OCP, droop, telemetry settings) - accelerates board bring-up and field reconfiguration |
| Black box fault recording | Logs timestamped fault events (OCP, OV, UV, thermal) with register snapshots - simplifies root-cause analysis in deployed systems |
Applications
| Server CPU Core VR | High-Density FPGA Power Delivery |
|---|---|
Use Scenario: Regulating core voltage for Cavium Thunder X2 processors in 1U/2U rack servers with strict transient response requirements. IC Role / Device Role / Timing Role: Dual-output multiphase controller managing 6+1 phase configuration; provides PMBus telemetry to BMC for dynamic power capping. Use Value: Meets Intel server-class transient specs with <100 ns response time and ±0.5% regulation accuracy under 50 A/µs load steps. | Use Scenario: Supplying multiple voltage rails (e.g., core, I/O, transceiver) for Xilinx UltraScale+ FPGAs in telecom line cards. IC Role / Device Role / Timing Role: Configurable dual-output controller operating in 4+3 mode; supports independent soft-start and sequencing per rail. Use Value: Enables single-chip solution for complex FPGA power trees with programmable droop and per-rail fault isolation. |
| Memory Subsystem VR (DDR4/LPDDR4) | ASIC Point-of-Load Regulation |
Use Scenario: Delivering tightly regulated 1.2 V DDR4 VDDQ and 2.5 V VPP rails in storage controllers with thermal-aware phase shedding. IC Role / Device Role / Timing Role: Dual-output controller using DCR sensing on both outputs; TMON0/TMON1 monitor DIMM temperature for adaptive current limiting. Use Value: Achieves ±5 mV setpoint accuracy at 1.2 V and supports dynamic VDDQ scaling via PMBus commands. | Use Scenario: Powering custom AI accelerator ASICs requiring 0.8 V @ 80 A with real-time current monitoring and fault logging. IC Role / Device Role / Timing Role: 7-phase single-output (7+0) configuration with ISL99227 smart power stages; black box records OCP events during inference bursts. Use Value: Provides cycle-by-cycle OCP resolution of 0.1 A and telemetry bandwidth sufficient for closed-loop thermal throttling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multiphase PWM controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL68137IRAZ | Supports AVSBus in addition to PMBus; identical 7-phase dual-output architecture and QFN-48 package | Targeted for AVS-enabled processors (e.g., certain ARM-based SoCs); lacks Cavium Thunder X2-specific optimizations | Select ISL68137IRAZ only when AVSBus dynamic voltage scaling is required and Cavium-specific features are unnecessary |
| MP2960AGQSE | Monolithic 6-phase controller with integrated MOSFET drivers; no PMBus 1.3 compliance; supports only single-output operation | Designed for cost-sensitive mid-range servers; lacks dual-output flexibility, black box logging, and TMON0/TMON1 thermal inputs | Choose MP2960AGQSE for simpler, lower-BOM-count single-rail applications where telemetry depth and configurability are secondary |
Compared with ISL68147IRAZ-T, ISL68137IRAZ adds AVSBus but removes Cavium-specific firmware optimizations, while MP2960AGQSE trades configurability and telemetry for integration and cost - making ISL68147IRAZ-T optimal for high-reliability, multi-rail server VRs demanding full PMBus observability and adaptive thermal management.
Availability
ISL68147IRAZ-T is available at Aetrix Electronics and suitable for networking equipment, telecom/datacom infrastructure, and server/storage power supply designs requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for ISL68147IRAZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and continues to develop and support its high-performance analog and power management portfolio for datacenter, industrial, and automotive markets.
The ISL68147IRAZ-T belongs to Renesas' digital multiphase controller product line, engineered specifically for high-current, low-voltage CPU/FPGA/ASIC point-of-load regulation in cloud-scale servers and high-end networking platforms.
FAQ
What is the maximum phase count supported by the ISL68147IRAZ-T?
The ISL68147IRAZ-T supports up to seven total phases across its two outputs (X+Y ≤ 7), with flexible allocation including 7+0, 6+1, 5+2, 4+3, and other combinations. When paired with the ISL6617A phase doubler, it enables up to 14-phase operation - verified in Figure 5 of the FN8880 datasheet. This scalability allows designers to match phase count precisely to load current and thermal constraints without overdesign.
Does the ISL68147IRAZ-T support both DCR and smart power stage current sensing?
Yes, the ISL68147IRAZ-T supports DCR sensing with integrated temperature compensation, resistor-based sensing, and direct interface to Intersil smart power stages like the ISL99227. Table 4 on page 19 and the "Current Sensing" section (page 13) confirm all three methods are fully supported, with dedicated CS/CSRTN pin pairs and automatic compensation algorithms for copper resistance drift.
How does the ISL68147IRAZ-T achieve ±0.5% closed-loop system accuracy?
The ISL68147IRAZ-T achieves ±0.5% closed-loop system accuracy through differential remote voltage sensing (VSEN0/RGND0 and VSEN1/RGND1), high-precision internal ADCs (±2.5% VINSEN accuracy, ±0.5% VOUT setpoint accuracy), and synthetic current modulation that eliminates phase current imbalance. Page 16 specifies this accuracy holds over full load, line, and temperature ranges - enabled by Kelvin sensing and on-die calibration.
Can the ISL68147IRAZ-T operate with only one output enabled?
Yes, the ISL68147IRAZ-T supports single-output operation in 7+0 configuration, where all seven phases drive Output 0 while Output 1 remains inactive. EN0 and EN1 pins allow independent enable/disable control, and PowerNavigator GUI permits full configuration of phase assignment, voltage, and protection settings per output - confirmed in the "Phase Configuration" section (page 12) and Figure 2 (6+1) and Figure 3 (4+3) typical applications.
What fault protection features are integrated into the ISL68147IRAZ-T?
The ISL68147IRAZ-T integrates pulse-by-pulse phase current limiting, total output current protection, input/output OV/UV detection, open voltage sense detection, thermal warning (TWARN), and black box fault logging. These are detailed in the "Fault Monitoring and Protection" section (pages 16–18), with independent thresholds programmable via PMBus - enabling robust, standards-compliant server VR designs without external supervision ICs.
ISL68147IRAZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- PWM Controller
- Voltage - Input:
- 3.3V ~ 3.3V
- Number of Outputs:
- 2
- Voltage - Output:
- 1.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-QFN (6x6)
ISL68147IRAZ-T FAQ
1.How can I place an order for ISL68147IRAZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL68147IRAZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL68147IRAZ-T reliable?
The price and inventory of ISL68147IRAZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL68147IRAZ-T is usually 5 days.
3.What payment methods are accepted for ISL68147IRAZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL68147IRAZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL68147IRAZ-T?
ISL68147IRAZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL68147IRAZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL68147IRAZ-T?
For technical support, including ISL68147IRAZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL68147IRAZ-T requirements.
6.How does Aetrix verify that ISL68147IRAZ-T is sourced from the original manufacturer or authorized distributors?
All ISL68147IRAZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL68147IRAZ-T meets industry standards.
7.What is the process for return or replacement of ISL68147IRAZ-T?
All ISL68147IRAZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL68147IRAZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL68147IRAZ-T part is unused and in its original packaging.
Return procedure for ISL68147IRAZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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