Renesas ISL8702AIBZ
- Part No.:
- ISL8702AIBZ
- Manufacturer:
- Renesas
- Category:
- Supervisors
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
ISL8702AIBZ.pdf
- Description:
- IC SUPERVISOR 4 CHANNEL 14SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL8702AIBZ from Renesas (formerly Intersil) is a quad-channel, adjustable power supply sequencer with integrated under/overvoltage monitoring for distributed rail supervision. It delivers four programmable enable outputs (ENABLE_A–D), supports 3.3V–24V input bias, provides UV/OV fault detection with 1.21V typical threshold, and features SEQ_EN-controlled on/off sequencing - used in FPGA, DSP, and multi-rail embedded systems requiring precise power-up/down timing.
For engineers reviewing the ISL8702AIBZ datasheet, ISL8702AIBZ pinout, ISL8702AIBZ application, or ISL8702AIBZ equivalent, this device enables robust voltage compliance validation, daisy-chainable sequencing up to >4 rails, and resistor- and capacitor-programmable delays (e.g., 3.5–240 ms between ENABLE outputs) without external logic or microcontroller intervention.
Technical Context
The ISL8702AIBZ implements a deterministic A→B→C→D sequencing order triggered by either auto-start (TIME capacitor charging) or external SEQ_EN assertion. Its internal 2.6µA TIME pin current source and 2.0V threshold comparator generate the initial delay, while TB/TC/TD pins each control subsequent inter-output delays via external resistors forming RC-based timing counters.
Voltage monitoring uses dedicated UV and OV pins with 104mV hysteresis and ±10nA input leakage; FAULT output asserts low when VIN falls outside the programmed window. All four ENABLE outputs are open-drain, active-high, and pull low below 1V VIN - ensuring fail-safe behavior during brown-out conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 3.3V to 24V nominal - powers IC and monitors any rail ≥1.22V via external divider |
| UV/OV Threshold | 1.21V typical rising - sets precise trip points for 12V±10% or custom rails using Ru/Rm/Rl dividers |
| TIME Pin Current | 2.6µA ± - charges external capacitor to generate 7.7ms–435ms delay to ENABLE_A start |
| Inter-Output Delay | 3.5ms–240ms per stage - set independently via RTB, RTC, RTD resistors (e.g., 3kΩ = 4.7ms, 120kΩ = 195ms) |
| FAULT Response | 30µs typical high-to-low - signals UV/OV violation with minimal latency for system-level fault handling |
| SEQ_EN Function | Active-high input - initiates or halts sequencing; enables controlled power-down in reverse D→C→B→A order |
| Package | 14-lead SOIC (M14.15) - industrial -40°C to +85°C operation with 110°C/W θJA |
Pinout & Package
ISL8702AIBZ is housed in a 14-lead narrow-body SOIC package (JEDEC MS-012, package drawing M14.15), optimized for surface-mount assembly and thermal performance in dense PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 ENABLE_A | Active-high open-drain sequenced output | First output released after TIME capacitor reaches 2.0V; pulls low if VIN < 1V |
| 2 ENABLE_B | Active-high open-drain sequenced output | Second output, delayed from ENABLE_A by RTB resistor; tracks same fail-safe behavior |
| 3 ENABLE_C | Active-high open-drain sequenced output | Third output, delayed from ENABLE_B by RTC resistor; maintains sequencing integrity |
| 4 ENABLE_D | Active-high open-drain sequenced output | Final output, delayed from ENABLE_C by RTD resistor; completes A→B→C→D ramp |
| 5 OV | Overvoltage sense input | Monitors upper rail limit; forces all ENABLE outputs low if voltage exceeds 1.21V threshold |
| 6 UV | Undervoltage sense input | Monitors lower rail limit; forces all ENABLE outputs low if voltage falls below 1.21V threshold |
| 7 GND | Ground reference | Common return for internal regulators, comparators, and output drivers |
| 8 FAULT | Open-drain fault reporting output | Pulled high externally; asserts low only when UV/OV window is violated |
| 9 SEQ_EN | Sequencing enable input | Active-high signal that starts or stops sequencing; internally pulled to ~2.4V |
| 10 TIME | Capacitor-based timing node | Sinks 2.6µA to charge external CTIME; delay to ENABLE_A determined by CTIME × 770kΩ |
| 11 TB | Timing resistor input (A→B) | Resistor to GND sets delay from ENABLE_A to ENABLE_B activation/deactivation |
| 12 TC | Timing resistor input (B→C) | Resistor to GND sets delay from ENABLE_B to ENABLE_C activation/deactivation |
| 13 TD | Timing resistor input (C→D) | Resistor to GND sets delay from ENABLE_C to ENABLE_D activation/deactivation |
| 14 VIN | Bias supply input | 3.3V–24V power source; requires 1µF local decoupling; powers internal 3.5V/1.17V regulators |
Key Features
| Feature | Design Value |
|---|---|
| Adjustable UV/OV monitoring | Independent 1.21V thresholds with 104mV hysteresis - enables precise 12V±10% or custom rail supervision |
| Four-stage programmable sequencing | A→B→C→D enable order with independent RTB/RTC/RTD resistor control - eliminates need for discrete timers or CPLDs |
| SEQ_EN-controlled bidirectional sequencing | Single-pin initiation of both power-up (A→D) and power-down (D→A) sequences - simplifies system-level power management |
| Low-quiescent current operation | 191µA at 3.3V VIN - minimizes standby power impact in always-on subsystems |
| Fail-safe ENABLE output behavior | All outputs pull low below 1V VIN - prevents false enabling during brown-out or cold-start conditions |
| Pb-free SOIC packaging | RoHS-compliant 14-lead SOIC (M14.15) - compatible with SnPb and Pb-free reflow profiles per J-STD-020 |
Applications
| FPGA Power Sequencing | DSP Core + I/O Rail Management |
|---|---|
Use Scenario: Sequencing 12V auxiliary, 3.3V I/O, 1.8V core, and 1.2V PLL rails for Xilinx Kintex-7 FPGA startup. IC Role / Device Role / Timing Role: ISL8702AIBZ acts as autonomous sequencer, enforcing strict voltage ramp order and validating 12V rail stability before releasing 1.2V PLL enable. Use Value: Prevents FPGA configuration failure by ensuring core voltage is stable before clock domain initialization, eliminating need for FPGA-internal POR workarounds. |
Use Scenario: Coordinating TI C6678 DSP power-up where 1.25V core must be valid before 3.3V SerDes and 1.8V memory interfaces. IC Role / Device Role / Timing Role: ISL8702AIBZ monitors 12V input rail and generates timed ENABLE signals to DC/DC converters controlling each voltage domain. Use Value: Guarantees 1.25V core reaches regulation before enabling high-speed transceivers - avoids SERDES lock failure and data corruption. |
| Industrial PLC Backplane Power Control | Medical Imaging Subsystem Sequencing |
Use Scenario: Managing hot-swap insertion of modular I/O cards into a 24V backplane with distributed 5V, 3.3V, and ±15V analog rails. IC Role / Device Role / Timing Role: ISL8702AIBZ serves as card-local sequencer, using SEQ_EN to gate sequencing until backplane voltage stabilizes and FAULT confirms no UV/OV event. Use Value: Enables safe hot-plug operation by delaying enable asserts until full rail compliance is verified - prevents inrush-induced bus droop and adjacent card reset. |
Use Scenario: Controlling power sequence for CT scanner detector ASICs requiring 1.5V digital, 2.5V analog, and ±5V bias supplies with tight timing margins. IC Role / Device Role / Timing Role: ISL8702AIBZ replaces FPGA-based sequencing logic, delivering deterministic sub-millisecond inter-rail delays via RTB/RTC/RTD resistors. Use Value: Eliminates firmware dependency and reduces BOM count by consolidating sequencing into single IC - improves diagnostic traceability and field reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power supply sequencing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSLR | Triple-output PMIC with fixed 1.2V/1.8V/2.8V LDOs; no UV/OV monitoring; no SEQ_EN control | Integrated regulation for low-current rails only; unsuitable for multi-vendor DC/DC coordination or fault-aware sequencing | Choose only if system uses only three fixed voltages and requires integrated regulation over sequencing flexibility |
| MAX16054ATL+ | Quad sequencer with fixed 100ms inter-delay; no resistor-programmable timing; FAULT only, no SEQ_EN | Limited timing granularity; lacks reverse sequencing capability; higher quiescent current (350µA) | Select when design requires simple, fixed-delay sequencing without fine-tuning or controlled shutdown |
Compared with TPS65023RSLR and MAX16054ATL+, the ISL8702AIBZ uniquely combines adjustable UV/OV monitoring, fully programmable inter-output delays via external resistors, and bidirectional SEQ_EN-triggered sequencing - making it optimal for complex, multi-rail systems demanding precision, adaptability, and fault resilience.
Availability
ISL8702AIBZ is available at Aetrix Electronics and suitable for FPGA power sequencing, DSP subsystem timing, and industrial PLC backplane control requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for ISL8702AIBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and continues to manufacture and support its high-performance analog and power management portfolio.
The ISL8702AIBZ belongs to the ISL870XA family of voltage-monitoring sequencers designed specifically for reliable, component-minimized power-up/down control in FPGA, DSP, and multi-rail embedded systems.
FAQ
What is the primary function of the ISL8702AIBZ in a power system?
The ISL8702AIBZ functions as a quad-channel, resistor- and capacitor-programmable power supply sequencer with integrated under/overvoltage monitoring. It ensures correct turn-on and turn-off order of multiple voltage rails - such as FPGA core, I/O, and auxiliary supplies - while continuously validating input rail compliance. Its design eliminates reliance on microcontrollers or complex logic for sequencing, making ISL8702AIBZ ideal for deterministic, fail-safe power management in high-reliability systems.
How does the ISL8702AIBZ handle undervoltage and overvoltage events?
The ISL8702AIBZ uses dedicated UV and OV pins with 1.21V typical threshold and 104mV hysteresis to monitor a distributed voltage rail. When the monitored voltage falls below UV or rises above OV, the FAULT output transitions high (open-drain, pulled externally), and all four ENABLE outputs are immediately forced low. This response occurs within 30µs, providing rapid fault signaling and preventing downstream circuitry from operating outside safe voltage limits - a critical safeguard in ISL8702AIBZ deployments.
Can the ISL8702AIBZ perform controlled power-down sequencing?
Yes - the ISL8702AIBZ supports bidirectional sequencing via its SEQ_EN input. When SEQ_EN is asserted high, it initiates standard A→B→C→D power-up. When SEQ_EN is deasserted, ISL8702AIBZ executes reverse-order power-down: D→C→B→A. Each inter-stage delay during shutdown is independently set by the same RTB, RTC, and RTD resistors used for power-up, ensuring symmetrical, predictable timing in both directions - a capability not found in most fixed-sequence alternatives.
What external components are required to configure the ISL8702AIBZ?
The ISL8702AIBZ requires minimal external components: one capacitor on the TIME pin (e.g., 10nF for ~8ms delay to ENABLE_A), three timing resistors (RTB, RTC, RTD) for inter-output delays, two divider resistors (Ru, Rm, Rl) for UV/OV threshold setting, a 1µF VIN decoupling capacitor, and pull-up resistors for ENABLE and FAULT outputs. No external clock, microcontroller, or additional logic is needed - the entire sequencing and monitoring functionality is self-contained within ISL8702AIBZ and these passive elements.
Is the ISL8702AIBZ pin-compatible with other members of the ISL870XA family?
No - while ISL8702AIBZ shares the same 14-lead SOIC package and pinout layout with ISL8700A, ISL8701A, ISL8703A, ISL8704A, and ISL8705A, functional pin assignments differ. For example, ISL8702AIBZ uses pin 9 as SEQ_EN, whereas ISL8704A uses it as SEQ_EN#, and ISL8700A/ISL8701A leave it unconnected. Similarly, ENABLE polarity (active-high vs. active-low) varies across variants. Therefore, ISL8702AIBZ is not a drop-in replacement for other ISL870XA parts without board-level verification and potential schematic updates.
ISL8702AIBZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Sequencer
- Number of Voltages Monitored:
- 4
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Open Drain or Open Collector
- Reset:
- Active High/Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
ISL8702AIBZ FAQ
1.How can I place an order for ISL8702AIBZ through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL8702AIBZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL8702AIBZ reliable?
The price and inventory of ISL8702AIBZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL8702AIBZ is usually 5 days.
3.What payment methods are accepted for ISL8702AIBZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL8702AIBZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL8702AIBZ?
ISL8702AIBZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL8702AIBZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL8702AIBZ?
For technical support, including ISL8702AIBZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL8702AIBZ requirements.
6.How does Aetrix verify that ISL8702AIBZ is sourced from the original manufacturer or authorized distributors?
All ISL8702AIBZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL8702AIBZ meets industry standards.
7.What is the process for return or replacement of ISL8702AIBZ?
All ISL8702AIBZ units undergo pre-shipment inspection (PSI). If there is an issue with ISL8702AIBZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL8702AIBZ part is unused and in its original packaging.
Return procedure for ISL8702AIBZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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