Renesas ISL90841UIV1427Z-TK
- Part No.:
- ISL90841UIV1427Z-TK
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ISL90841UIV1427Z-TK.pdf
- Description:
- IC DGT POT 50KOHM 256TAP 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL90841UIV1427Z-TK from Renesas (formerly Intersil) is a quad digitally controlled potentiometer (XDCP™) IC with I²C interface, 50kΩ total resistance per channel, 256-tap resolution, and 14-lead TSSOP package. It operates from 2.7V to 5.5V, delivers <5µA standby current, and functions as precision voltage dividers or rheostats in analog signal conditioning circuits.
For engineers reviewing the ISL90841UIV1427Z-TK datasheet, ISL90841UIV1427Z-TK pinout, ISL90841UIV1427Z-TK application, or ISL90841UIV1427Z-TK equivalent, key selection criteria include I²C address configuration (A0/A1), wiper resistance (70Ω typ.), DCP matching (±2 LSB), ratiometric temperature coefficient (±4 ppm/°C), and volatile wiper register behavior on power-up (reset to 0x80).
Technical Context
The ISL90841UIV1427Z-TK integrates four independent CMOS-switched resistor ladder networks, each with an 8-bit volatile Wiper Register (WR) directly accessible via I²C. All RH terminals connect internally to VCC-side nodes while RW terminals serve as programmable taps referenced to GND - enabling true voltage divider operation without external biasing.
Its I²C slave interface supports standard-mode (400kHz) timing, uses A0/A1 pins for device addressing (00h–03h), and implements ACK-based protocol compliance with START/STOP framing. Power-on reset initializes all WRs to 0x80, placing wipers at mid-scale (128/255) for predictable startup behavior in gain/offset calibration systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total resistance | 50kΩ per DCP - sets full-scale voltage division ratio and maximum rheostat resistance range. |
| Resolution | 256 taps (8-bit) - enables 0.4% step resolution for fine analog control in sensor biasing or DAC trimming. |
| Wiper resistance | 70Ω typical @ 3.3V - limits insertion error and thermal noise in low-level signal paths. |
| Standby current | <5µA max @ 5.5V - supports ultra-low-power battery-operated systems during idle periods. |
| I²C clock frequency | 400kHz - compatible with standard-mode controllers without requiring high-speed mode hardware. |
| Integral non-linearity | ±1 LSB in voltage divider mode - ensures monotonic output and ≤0.4% transfer function deviation across full scale. |
| DCP-to-DCP matching | ±2 LSB - guarantees consistent gain/attenuation across channels in multi-path signal processing. |
Pinout & Package
Package: 14-lead TSSOP (V14), RoHS-compliant, Pb-free plus anneal finish, 4.4mm × 5.0mm body, 0.65mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RH0–RH3 | "High" terminal of DCP0–DCP3 | Connects to VCC or signal source; defines upper rail of voltage divider or one end of rheostat. |
| RW0–RW3 | "Wiper" terminal of DCP0–DCP3 | Programmable tap output; used for variable gain, offset, or feedback node injection. |
| VCC | Power supply input | Supplies core logic and resistor ladder; accepts 2.7V–5.5V with internal regulation for stable DCP operation. |
| GND | Ground reference | Common return for all DCP low sides and digital interface; must be low-impedance for noise immunity. |
| SCL / SDA | I²C clock and bidirectional data | Enable serial configuration without dedicated GPIO; require external pull-ups (2–20kΩ depending on bus capacitance). |
| A0 / A1 | I²C device address inputs | Set slave address bits (00h–03h); allow up to four ISL90841 devices on same bus without address conflict. |
Key Features
| Feature | Design Value |
|---|---|
| Quad independent DCPs | Four isolated 50kΩ potentiometers share one I²C interface - reduces board space vs discrete solutions and enables synchronized parameter tuning. |
| Volatile wiper registers | All WRs reset to 0x80 on power-up - ensures repeatable mid-scale startup for gain/offset calibration without host initialization delay. |
| Low wiper resistance | 70Ω typical - minimizes voltage drop and thermal drift in precision current-sensing or op-amp feedback paths. |
| Ratiometric tempco | ±4 ppm/°C - maintains stable voltage division ratio over temperature, critical for sensor excitation and ADC reference scaling. |
| DCP matching | ±2 LSB between any two channels - supports matched gain control in differential amplifiers or multi-channel audio level adjustment. |
Applications
| Instrumentation Gain Calibration | Sensor Excitation Biasing |
|---|---|
|
Use Scenario: Precision instrumentation amplifier with programmable gain setting via feedback network. IC Role / Device Role / Timing Role: ISL90841UIV1427Z-TK acts as digitally adjustable feedback resistor in dual-op-amp topology, replacing mechanical trimmers. Use Value: Enables remote recalibration without hardware change; ±2 LSB matching ensures identical gain across differential channels. |
Use Scenario: Bridge sensor (e.g., load cell, RTD) requiring stable excitation voltage with temperature compensation. IC Role / Device Role / Timing Role: ISL90841UIV1427Z-TK configures voltage divider to set excitation level; ratiometric tempco tracks sensor drift. Use Value: Eliminates analog drift sources; 0.4% resolution allows sub-0.1% excitation accuracy over industrial temperature range. |
| Audio Channel Level Control | ADC Reference Scaling |
|
Use Scenario: Multi-channel audio mixer with independent digital volume control per input path. IC Role / Device Role / Timing Role: ISL90841UIV1427Z-TK serves as ground-referenced rheostat in op-amp attenuator stage before summing node. Use Value: Provides click-free adjustment via I²C; 256-step resolution achieves 0.5dB steps across 78dB dynamic range. |
Use Scenario: High-resolution SAR ADC requiring programmable reference voltage scaling for varying input ranges. IC Role / Device Role / Timing Role: ISL90841UIV1427Z-TK forms precision voltage divider between VREF and GND to generate adjustable reference. Use Value: ±1 LSB INL preserves ADC effective resolution; low wiper resistance prevents loading-induced reference droop. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5242BRUZ10 | 10kΩ total resistance, I²C interface, ±30% RH tolerance, no ratiometric tempco spec | Better suited for low-resistance rheostat use; less precise for voltage divider applications requiring tight ratio stability | Select when lower end-to-end resistance and higher wiper current (±20mA) are required over temperature-stable ratio performance |
| MCP42010-I/ST | Dual-channel (not quad), SPI interface, 10kΩ/50kΩ options, 10-bit resolution, ±20% RH tolerance | Requires separate SPI lines per device; lacks DCP-to-DCP matching spec and ratiometric tempco guarantee | Choose for designs already using SPI peripherals and needing higher resolution, accepting reduced channel density and matching capability |
Compared with AD5242BRUZ10 and MCP42010-I/ST, the ISL90841UIV1427Z-TK uniquely delivers quad-channel integration, guaranteed ±2 LSB matching, ±4 ppm/°C ratiometric tempco, and 50kΩ precision resistance - making it optimal for multi-channel analog signal conditioning where ratio stability and inter-channel consistency are critical.
Availability
ISL90841UIV1427Z-TK is available at Aetrix Electronics and suitable for instrumentation gain calibration, sensor excitation biasing, audio channel level control, and ADC reference scaling requiring stable component supply and long-term design-in support.
Supply support for ISL90841UIV1427Z-TK includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation acquired Intersil in 2017 and continues to manufacture, test, and support legacy Intersil precision analog products under ISO9001 quality systems.
The ISL90841UIV1427Z-TK belongs to Renesas' XDCP™ (eXternally Digitally Controlled Potentiometer) family, designed specifically for replacing mechanical potentiometers in industrial, medical, and test equipment where remote programmability, repeatability, and long-term stability are essential.
FAQ
What is the default wiper position of the ISL90841UIV1427Z-TK after power-up?
The ISL90841UIV1427Z-TK resets all four wiper registers to 0x80 (128 decimal) on power-up, positioning each wiper at mid-scale - i.e., approximately 50% of the total resistance between RH and GND. This behavior is hardwired and does not require I²C initialization, ensuring predictable startup in gain/offset calibration circuits. The ISL90841UIV1427Z-TK maintains this state until explicitly reprogrammed via its I²C interface.
Does the ISL90841UIV1427Z-TK support non-volatile wiper storage?
No, the ISL90841UIV1427Z-TK uses volatile wiper registers only - wiper positions are lost when VCC is removed. It does not include EEPROM or flash memory for persistent storage. To retain settings across power cycles, the host controller must reprogram the ISL90841UIV1427Z-TK's wiper registers during system boot. This design prioritizes speed, low power, and cost over non-volatility.
Can the ISL90841UIV1427Z-TK be used in rheostat mode with both terminals floating?
No - the ISL90841UIV1427Z-TK requires one terminal (GND) to be tied to system ground per DCP, as stated in the datasheet. Its architecture connects the "low" side of each potentiometer internally to GND; only RH and RW are user-accessible. Using it as a two-terminal variable resistor mandates connecting RH to a defined voltage (e.g., VCC or signal source) and RW to the circuit node, with GND serving as the fixed reference. Floating configurations are not supported.
What is the maximum allowable voltage across any DCP terminal of the ISL90841UIV1427Z-TK?
The absolute maximum voltage across any DCP terminal (RH or RW) relative to GND is limited to VCC, per the datasheet's Absolute Maximum Ratings. Exceeding VCC risks latch-up or permanent damage. For example, with VCC = 3.3V, RH and RW must remain within 0V to 3.3V. Additionally, the power rating per DCP is capped at 5mW, constraining usable voltage/current combinations - e.g., at 50kΩ, maximum continuous wiper current is ±3.0mA.
How does the ISL90841UIV1427Z-TK handle I²C bus contention or incomplete transactions?
The ISL90841UIV1427Z-TK requires a valid START condition followed by correct Identification and Address Bytes before responding with ACK. If a transaction is interrupted (e.g., missing STOP, NACK, or clock stretch timeout), the device remains in its last known state - wiper positions are unaffected. Unrecognized commands or malformed bytes are ignored, and the I²C interface returns to listening mode. No internal state corruption occurs, and the ISL90841UIV1427Z-TK resumes normal operation upon next valid START.
ISL90841UIV1427Z-TK Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Rheostat
- Number of Circuits:
- 4
- Number of Taps:
- 256
- Resistance (Ohms):
- 50k
- Interface:
- I2C
- Memory Type:
- Volatile
- Voltage - Supply:
- 2.7V ~ 5.5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±45ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 14-TSSOP
- Operating Temperature:
- -40°C ~ 85°C
- Resistance - Wiper (Ohms) (Typ):
- 70
ISL90841UIV1427Z-TK FAQ
1.How can I place an order for ISL90841UIV1427Z-TK through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL90841UIV1427Z-TK on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL90841UIV1427Z-TK reliable?
The price and inventory of ISL90841UIV1427Z-TK are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL90841UIV1427Z-TK is usually 5 days.
3.What payment methods are accepted for ISL90841UIV1427Z-TK?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL90841UIV1427Z-TK transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL90841UIV1427Z-TK?
ISL90841UIV1427Z-TK orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL90841UIV1427Z-TK order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL90841UIV1427Z-TK?
For technical support, including ISL90841UIV1427Z-TK datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL90841UIV1427Z-TK requirements.
6.How does Aetrix verify that ISL90841UIV1427Z-TK is sourced from the original manufacturer or authorized distributors?
All ISL90841UIV1427Z-TK products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL90841UIV1427Z-TK meets industry standards.
7.What is the process for return or replacement of ISL90841UIV1427Z-TK?
All ISL90841UIV1427Z-TK units undergo pre-shipment inspection (PSI). If there is an issue with ISL90841UIV1427Z-TK, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL90841UIV1427Z-TK part is unused and in its original packaging.
Return procedure for ISL90841UIV1427Z-TK:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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