My Inquiry
My Account
Renesas ISL91301AIIZ-T
- Part No.:
- ISL91301AIIZ-T
- Manufacturer:
- Renesas
- Package:
- -
- Datasheet:
-
ISL91301AIIZ-T.pdf
- Description:
- IC REG
- Quantity:
- Payment:
- Shipping:
Inventory:2,277
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ISL91301AIIZ-T from Renesas is a triple-output, 4-phase programmable Power Management IC (PMIC) with 2+1+1 phase configuration, delivering up to 8A on VOUT1 (2-phase), 3A on VOUT2, and 3A on VOUT3. It integrates synchronous buck controllers with R5 proprietary control architecture, supports I²C/SPI programming, and operates from 2.5V–5.5V input for mobile SoC power delivery in smartphones and AI processors.
For engineers reviewing the ISL91301AIIZ-T datasheet, ISL91301AIIZ-T pinout, ISL91301AIIZ-T application, or ISL91301AIIZ-T equivalent, key selection criteria include its 42-ball WLCSP package, ±0.7% output accuracy with remote sensing, 4MHz switching frequency, dynamic voltage scaling per rail, and support for 3A/phase (VIN_SEL = GND) or 4A/phase (VIN_SEL = AVIN) operation.
Technical Context
The ISL91301AIIZ-T implements Renesas' R5 control architecture across four integrated buck controllers, enabling seamless CCM/DCM transitions and ultra-fast transient response (e.g., 50A/µs per phase). Its 2+1+1 phase assignment allocates two phases to VOUT1 and one each to VOUT2 and VOUT3, supporting independent DVS and soft-start sequencing.
It features four MPIOs and two GPIOs configurable for SPI/I²C communication, hardware enable/DVS pin modes, and PGOOD outputs. The device uses internal low-RDS(ON) MOSFETs (55mΩ HS / 14mΩ LS), supports programmable PWM frequency (2–6MHz), and includes comprehensive protection: UV/OV/OC/OT with ±35mV OVP/UVP thresholds and 143°C thermal shutdown.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Configuration | Triple output (2+1+1 phase): VOUT1 = 2-phase (up to 8A), VOUT2/VOUT3 = single-phase (3A each) |
| Input Voltage Range | 2.5V–5.5V (VIN_SEL = GND) or 2.8V–5.5V (VIN_SEL = AVIN); defines max per-phase current capability |
| Switching Frequency | Programmable 2–6MHz; enables use of sub-300nH inductors and compact ceramic capacitors |
| Output Voltage Range | 0.3V–2.0V (I²C-programmable in 1.2–2.0mV steps); supports core voltage scaling for mobile SoCs |
| Output Accuracy | ±0.7% over –40°C to +85°C with remote sensing; ensures stable CPU/GPU rail regulation |
| Efficiency | 93% at 3.8VIN/1.8VOUT; achieved via synchronous rectification and Diode Emulation mode |
| Quiescent Current | 17µA (all bucks disabled, EN high); critical for battery runtime in always-on subsystems |
Pinout & Package
Package: 2.570mm × 2.919mm, 42-ball WLCSP with 0.4mm pitch, RoHS-compliant, MSL3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PVIN_A, PVIN_B, PVIN_C, PVIN_D | Power input per phase | Independent supply inputs for each buck stage; decoupling required per pin |
| PH_A, PH_B, PH_C, PH_D | Switching node output | High-frequency gate drive nodes connecting to external inductors; layout-sensitive |
| PGND_A–PGND_D | Phase ground return | Dedicated ground paths per phase to minimize noise coupling and improve EMI |
| VOUT1–VOUT4, RTN1–RTN4 | Remote voltage/ground sense | Enables Kelvin sensing for ±0.7% accuracy; RTN pins must connect near load |
| VIN_SEL | Input voltage range select | Tie to AVIN for 2.8–5.5V/4A-phase mode; tie to GND for 2.5–5.5V/3A-phase mode |
| MPIO0–MPIO3, GPIO0–GPIO1 | Configurable I/O | Support SPI/I²C, DVS control, PGOOD, or hardware enable functions per pin mode table |
Key Features
| Feature | Design Value |
|---|---|
| R5 proprietary control scheme | Eliminates external compensation, delivers <10µs transient recovery and tight load regulation |
| Independent Dynamic Voltage Scaling | Each output adjustable in real time via I²C/SPI; supports adaptive SoC power states |
| Automatic Diode Emulation & Pulse Skipping | Extends battery life in light-load conditions without audible coil whine |
| Four-buck fault protection | Per-rail UV/OV/OC detection with latched or auto-retry behavior configurable via registers |
| Flexible pin mode configuration | Eight I/O modes including SPI master/slave, I²C with PGOOD, and hardware DVS control |
Applications
| Smartphones | AI Accelerator Modules |
|---|---|
Use Scenario: Powering application processor cores (CPU/GPU/NPU) with dynamic voltage/frequency scaling. IC Role / Device Role / Timing Role: Triple-rail PMIC delivering sequenced, independently regulated voltages with fast transient response. Use Value: Enables 50A/µs load steps during burst-mode AI inference while maintaining ±0.7% output accuracy. | Use Scenario: Supplying multiple voltage domains (core, memory, I/O) in edge AI inference accelerators. IC Role / Device Role / Timing Role: Configurable 2+1+1 phase topology provides high-current core rail and dedicated lower-current rails. Use Value: Reduces solution size by integrating four buck controllers and MOSFETs in 2.57×2.92mm WLCSP. |
| AR/VR Wearables | Optical Transceiver DSPs |
Use Scenario: Powering compact SoCs and image signal processors in battery-constrained AR glasses. IC Role / Device Role / Timing Role: Ultra-low quiescent current (17µA) PMIC with I²C-controlled DVS for display and sensor subsystems. Use Value: Extends battery runtime via Diode Emulation mode and 93% peak efficiency at 3.8VIN/1.8VOUT. | Use Scenario: Regulating DSP, laser driver, and analog front-end supplies in 100G optical modules. IC Role / Device Role / Timing Role: High-accuracy, low-noise triple-output regulator with remote sensing for sensitive analog circuits. Use Value: Maintains ±0.7% output stability across temperature and load, critical for laser bias accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL91301BIIZ-T | Quad-output (1+1+1+1 phase), same 42-ball WLCSP package and R5 control architecture | Supports four independent rails instead of three; no 2-phase VOUT1 capability | Select when system requires four distinct voltage domains rather than high-current dual-phase core rail |
| ISL91211AIIZ-T | Triple-output (2+1+1), 54-ball WLCSP, 5A/phase capability, wider VIN range (2.3V–5.5V) | Larger package, higher current, different pinout; not pin-compatible | Choose for higher current demand (>4A/phase) or extended low-VIN operation below 2.5V |
Compared with ISL91301BIIZ-T, the ISL91301AIIZ-T provides higher per-rail current on VOUT1 via 2-phase interleaving but lacks a fourth output; versus ISL91211AIIZ-T, it offers smaller footprint and lower cost at the expense of reduced current headroom and VIN range.
Availability
ISL91301AIIZ-T is available at Aetrix Electronics and suitable for smartphones, AI accelerator modules, and AR/VR wearables requiring stable component supply, full lifecycle support, and traceable sourcing.
Supply support for ISL91301AIIZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and consumer markets.
The ISL91301A belongs to Renesas' high-density, multi-rail PMIC product line designed specifically for space-constrained mobile and edge AI platforms requiring programmable, high-efficiency power delivery with minimal external components.
FAQ
What is the maximum continuous output current per phase for ISL91301AIIZ-T?
The ISL91301AIIZ-T delivers 4A per phase when VIN_SEL is tied to AVIN (2.8V–5.5V input range) and 3A per phase when VIN_SEL is tied to GND (2.5V–5.5V input range). In its default 2+1+1 configuration, this yields up to 8A on VOUT1 (2-phase) and 3A each on VOUT2 and VOUT3.
How does the R5 control architecture in ISL91301AIIZ-T improve transient response?
The R5 control architecture in ISL91301AIIZ-T enables ultra-fast transient response-up to 50A/µs per phase-by eliminating external compensation components, optimizing loop bandwidth, and ensuring seamless transitions between CCM and DCM. This maintains tight output regulation during rapid load steps typical in mobile SoC burst-mode operation.
Can ISL91301AIIZ-T support independent dynamic voltage scaling on all three outputs?
Yes, the ISL91301AIIZ-T supports Independent Dynamic Voltage Scaling (DVS) on all three outputs via I²C or SPI commands. Each rail's voltage can be adjusted in real time with 10-bit resolution (1.2–2.0mV step size), enabling coordinated power-state transitions for CPU, GPU, and memory subsystems.
What package type and dimensions does ISL91301AIIZ-T use?
The ISL91301AIIZ-T uses a 42-ball WLCSP package measuring 2.570mm × 2.919mm with 0.4mm ball pitch. It is RoHS-compliant, Pb-free, and rated MSL3, optimized for ultra-compact PCB layouts in mobile and wearable devices.
Does ISL91301AIIZ-T include built-in protection features, and what are they?
Yes, ISL91301AIIZ-T includes comprehensive protection: overvoltage (±35mV threshold accuracy), undervoltage, overcurrent (per-phase), and overtemperature (143°C shutdown with 55°C hysteresis). Faults trigger interrupt signaling and configurable latch/auto-retry behavior via register settings.
ISL91301AIIZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- -
- Output Configuration:
- -
- Topology:
- -
- Output Type:
- -
- Number of Outputs:
- -
- Voltage - Input (Min):
- -
- Voltage - Input (Max):
- -
- Voltage - Output (Min/Fixed):
- -
- Voltage - Output (Max):
- -
- Current - Output:
- -
- Frequency - Switching:
- -
- Synchronous Rectifier:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
ISL91301AIIZ-T FAQ
1.How can I place an order for ISL91301AIIZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL91301AIIZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL91301AIIZ-T reliable?
The price and inventory of ISL91301AIIZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL91301AIIZ-T is usually 5 days.
3.What payment methods are accepted for ISL91301AIIZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL91301AIIZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL91301AIIZ-T?
ISL91301AIIZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL91301AIIZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL91301AIIZ-T?
For technical support, including ISL91301AIIZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL91301AIIZ-T requirements.
6.How does Aetrix verify that ISL91301AIIZ-T is sourced from the original manufacturer or authorized distributors?
All ISL91301AIIZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL91301AIIZ-T meets industry standards.
7.What is the process for return or replacement of ISL91301AIIZ-T?
All ISL91301AIIZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL91301AIIZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL91301AIIZ-T part is unused and in its original packaging.
Return procedure for ISL91301AIIZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ISL91301AIIZ-T Tags
-
TPS562201DDCR
Texas Instruments
-
MC34063ABD-TR
STMicroelectronics
-
TPS561201DDCR
Texas Instruments
-
MC33063ADR
Texas Instruments
-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments
-
AP3012KTR-G1
Diodes Incorporated
-
TLV61048DBVR
Texas Instruments
-
AZ34063UMTR-G1
Diodes Incorporated
-
TPS562200DDCR
Texas Instruments
-
AP62300TWU-7
Diodes Incorporated
-
MC34063EBD-TR
STMicroelectronics
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
