Renesas ISL9305IRTBFNCZ-T
- Part No.:
- ISL9305IRTBFNCZ-T
- Manufacturer:
- Renesas
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-WQFN Exposed Pad
- Datasheet:
-
ISL9305IRTBFNCZ-T.pdf
- Description:
- IC REG QUAD BUCK/LNR 3MHZ 16TQFN
- Quantity:
- Payment:

- Shipping:

Inventory:6,000
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Product details
Overview
ISL9305IRTBFNCZ-T from Renesas Electronics is a dual-output PMIC integrating two 3MHz synchronous step-down converters (800mA each) and two low-input LDOs (300mA each), with I²C programmability for dynamic voltage scaling in battery-powered microprocessor systems. It supports 2.3V–5.5V input, delivers factory-fixed DCD1/DCD2 outputs of 1.5V/2.5V and LDO1/LDO2 outputs of 3.3V/1.8V, and operates across –40°C to +85°C in portable electronics.
For engineers reviewing the ISL9305IRTBFNCZ-T datasheet, ISL9305IRTBFNCZ-T pinout, ISL9305IRTBFNCZ-T application, or ISL9305IRTBFNCZ-T equivalent, key selection criteria include I²C-configurable slew rate (0.225–28.8 mV/µs), skip-mode efficiency optimization, PGOOD delay programming (1–200 ms), and thermal shutdown at 155°C with 30°C hysteresis.
Technical Context
The ISL9305IRTBFNCZ-T implements peak-current-mode PWM control for both buck converters, enabling fast transient response and pulse-by-pulse current limiting. Its 3MHz switching frequency permits ultra-compact external LC filtering (e.g., 1.5µH inductors and 4.7µF output capacitors), while integrated bleeding resistors (115Ω typ.) support active output discharge during disable.
I²C interface operates at up to 400 kbps with 7-bit slave address 0x68; registers enable independent control of DCD/LDO enable states, PFM/PWM mode selection, phase alignment (in-phase or 180° out-of-phase), and ultrasonic operation under light load. Power-good monitoring uses an open-drain DCDPG pin with programmable delay and ±3% voltage window thresholds.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.3V–5.5V for DCD1/DCD2; 1.5V–5.5V for LDO1/LDO2 - enables direct Li-ion/Li-Polymer battery input without pre-regulation |
| DCD Output Current | 800mA per channel - sufficient for DSP core or memory rail power in smartphones |
| LDO Output Current | 300mA per channel - supports I/O or auxiliary rails with low-noise (<45 µVRMS) regulation |
| Switching Frequency | 2.6–3.4 MHz (typ. 3 MHz) - allows use of sub-2mm footprint inductors and reduces EMI fundamental frequency |
| I²C Interface Speed | Up to 400 kbps - supports real-time dynamic voltage scaling during processor DVFS transitions |
| Thermal Shutdown | 155°C activation with 30°C hysteresis - ensures safe operation under sustained high-load or poor PCB thermal design |
| Quiescent Current | 50 µA typ. with both DCDs enabled in skip mode - extends battery runtime in standby states |
Pinout & Package
The ISL9305IRTBFNCZ-T is housed in a thermally enhanced 4mm × 4mm, 16-lead TQFN package with exposed E-pad for PCB-level heat dissipation. Pin assignments are validated per FN7605 Rev 2.00, Page 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VINDCD1 (Pin 1) | Main input supply for DCD1 and internal circuitry | Primary power entry point; must be decoupled with ≥10µF ceramic capacitor near pin |
| FB1 (Pin 2) | Feedback node for DCD1 output voltage regulation | Connected directly to DCD1 output in fixed-voltage version (ISL9305IRTBFNCZ-T); no external resistor divider required |
| SCLK (Pin 3) | I²C clock input | Requires external pull-up to VDDIO; timing compliant with standard-mode (100 kbps) and fast-mode (400 kbps) I²C |
| SDAT (Pin 4) | I²C data bidirectional line | Open-drain structure; shares pull-up with SCLK; supports register read/write and status polling |
| VINLDO1 (Pin 5) | Input supply for LDO1 | Can be powered from battery or DCD1 output; supports input as low as 1.5V |
| VOLDO1 (Pin 6) | LDO1 regulated output (factory-set 3.3V) | Fixed 3.3V output; no external components needed; supplies I/O or interface logic rails |
| VOLDO2 (Pin 7) | LDO2 regulated output (factory-set 1.8V) | Fixed 1.8V output; optimized for low-noise analog or memory interface circuits |
| VINLDO2 (Pin 8) | Input supply for LDO2 | Independent input path allows flexible rail sequencing and source selection |
| GNDLDO (Pin 9) | Power ground for both LDOs | Must be connected to low-impedance ground plane; separate from DCD grounds to minimize noise coupling |
| DCDPG (Pin 10) | Open-drain power-good indicator for DCD1/DCD2 | Asserts low if either converter output deviates >±3% from nominal; delay programmable from 1–200 ms via I²C |
| FB2 (Pin 11) | Feedback node for DCD2 output voltage regulation | Direct-connected to DCD2 output in this fixed-version part; eliminates external resistor network |
| VINDCD2 (Pin 12) | Input supply for DCD2 | Shares same input range as DCD1; supports independent input sourcing if required |
| SW2 (Pin 13) | DCD2 switching node | High dv/dt node; requires short, wide trace to inductor; keep away from sensitive analog traces |
| GNDDCD2 (Pin 14) | Power ground for DCD2 | Must be tied to dedicated ground pour under IC; connects to E-pad for thermal conduction |
| GNDDCD1 (Pin 15) | Power ground for DCD1 | Separate ground return minimizes cross-talk between buck stages; routed independently to E-pad |
| SW1 (Pin 16) | DCD1 switching node | Same layout constraints as SW2; forms critical high-frequency loop with L1 and COUT |
Key Features
| Feature | Design Value |
|---|---|
| Dual 3MHz synchronous buck converters | Enables <2 mm² total passive area per channel using 1.5µH inductors and 4.7µF output caps |
| I²C-programmable output voltage slew rate | Eight selectable rates (0.225–28.8 mV/µs) allow precise control of voltage ramp time during DVFS transitions |
| Configurable skip mode / forced PWM operation | Extends light-load efficiency to >85% while maintaining low-noise operation in forced PWM for RF-sensitive subsystems |
| Active output discharge via internal 115Ω bleed resistor | Ensures rapid, controlled discharge of DCD outputs on disable-eliminates need for external discharge FETs |
| Programmable DCD power-good delay (1–200 ms) | Allows synchronization with system power sequencing requirements without external timers or logic |
| Thermal shutdown with 30°C hysteresis | Prevents thermal runaway during overload or poor heatsinking; automatic recovery avoids manual reset |
Applications
| Smartphone Application | DSP Core Power |
|---|---|
Use Scenario: Dual-rail power delivery for application processor (1.5V core, 2.5V I/O) and peripheral LDOs (3.3V interface, 1.8V sensor interface) in compact smartphone PCBs. IC Role / Device Role / Timing Role: Integrated mini-PMIC providing sequenced, I²C-controlled voltage rails with PGOOD coordination for boot integrity. Use Value: Reduces BOM count by replacing four discrete regulators; factory-fixed outputs eliminate calibration overhead in high-volume assembly. | Use Scenario: Powering TI C6000 or Analog Devices SHARC DSP cores requiring tightly regulated, low-noise 1.5V/2.5V supplies with dynamic voltage scaling. IC Role / Device Role / Timing Role: Dual-buck regulator delivering synchronized, slew-rate-controlled outputs during frequency transitions. Use Value: 3MHz switching enables <100 ns output voltage step resolution; skip mode maintains >90% efficiency at 10 mA load. |
| Portable Media Player | Li-ion Battery-Powered Instrument |
Use Scenario: Power management for ARM-based media players with LCD backlight (DCD2), SoC core (DCD1), audio codec (LDO1), and touch controller (LDO2). IC Role / Device Role / Timing Role: Single-chip solution managing rail sequencing, battery voltage tracking, and I²C-based runtime reconfiguration. Use Value: 50 µA quiescent current in skip mode extends playback time; 1.5V/2.5V/3.3V/1.8V factory settings match common media SoC voltage maps. | Use Scenario: Precision handheld test equipment (e.g., multimeter, spectrum analyzer) powered by single-cell Li-ion with strict noise and thermal limits. IC Role / Device Role / Timing Role: Low-noise LDOs (45 µVRMS) supply analog front-end; buck converters power digital processing with thermal-aware throttling. Use Value: Active discharge prevents floating outputs during sleep; thermal shutdown at 155°C protects against enclosure overheating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-buck + dual-LDO PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Triple 600mA buck + triple LDO; 2.5–6V input; no I²C slew rate control; fixed 2.4MHz switching | Higher integration but less flexible voltage ramp control; lacks programmable PGOOD delay | Preferred when needing third buck rail and higher input voltage tolerance; not suitable for fine-grained DVFS timing control |
| RT8070ZSP | Dual 1.2A buck + dual 300mA LDO; 2.7–5.5V input; I²C interface; 2MHz switching; no active discharge | Higher current capability but lower switching frequency increases passive size; no internal bleed resistor | Chosen for higher load margin in industrial applications; requires external discharge circuitry if fast turn-off is needed |
Compared with TPS65023RSBR and RT8070ZSP, the ISL9305IRTBFNCZ-T offers superior dynamic voltage control granularity (25mV/step, 8 slew rates), integrated active discharge, and tighter thermal protection-making it optimal for space-constrained, battery-life-critical portable designs where precise rail sequencing and low-light-load efficiency are mandatory.
Availability
ISL9305IRTBFNCZ-T is available at Aetrix Electronics and suitable for smartphone power management, DSP core supply, portable media player design, and Li-ion battery-powered instrumentation requiring stable component supply and full lifecycle support.
Supply support for ISL9305IRTBFNCZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT markets, with deep expertise in power management and mixed-signal design.
The ISL9305 series belongs to Renesas' mini-PMIC product line, engineered specifically for space- and efficiency-constrained portable electronics that demand multi-rail, I²C-configurable power with minimal external components.
FAQ
What are the factory-programmed output voltages for ISL9305IRTBFNCZ-T?
The ISL9305IRTBFNCZ-T has factory-fixed outputs: DCD1 = 1.5V, DCD2 = 2.5V, LDO1 = 3.3V, and LDO2 = 1.8V. These values are confirmed in the Ordering Information table (Page 4 of FN7605 Rev 2.00) and require no external feedback resistors. The I²C interface retains full programmability within the 0.825–3.6V (DCD) and 0.9–3.6V (LDO) ranges, but default startup behavior follows these preset values.
Does ISL9305IRTBFNCZ-T support independent enable/disable control of each regulator?
Yes, the ISL9305IRTBFNCZ-T provides individual enable/disable control for all four regulators via the SYS_PARAMETER register (address 0x05h). Bits B0–B3 control DCD1_EN, DCD2_EN, LDO1_EN, and LDO2_EN respectively. This allows precise power sequencing-for example, enabling DCD1 first, waiting for PGOOD assertion, then enabling LDO1-without external GPIOs or timing circuits.
What is the maximum I²C clock frequency supported by ISL9305IRTBFNCZ-T?
The ISL9305IRTBFNCZ-T supports standard-mode (100 kbps) and fast-mode (400 kbps) I²C operation, as specified in Section "I2C Compatible Interface" (Page 9). The 400 kbps maximum enables rapid configuration updates during processor DVFS events. Pull-up resistors must be sized per bus capacitance, and level-shifting is required only if host and ISL9305IRTBFNCZ-T operate at different VDDIO levels.
How does the DCDPG pin behave when only one buck converter is enabled?
When only DCD1 or DCD2 is enabled, the DCDPG pin monitors only that active converter's output. Per Page 8 of FN7605 Rev 2.00, if DCD1 is enabled and DCD2 disabled, DCDPG asserts high (after programmed delay) only when DCD1's output is within ±3% of its nominal voltage. If DCD1 falls outside that window, DCDPG pulls low. The same applies for DCD2-only operation-ensuring accurate fault reporting even in partial-enable configurations.
Is the exposed thermal pad of ISL9305IRTBFNCZ-T required to be soldered to PCB ground?
Yes, the exposed E-pad of the ISL9305IRTBFNCZ-T must be soldered to a solid PCB ground plane with ≥9 thermal vias (per Figure 4, Page 8). This connection is essential for thermal performance: θJC is 5°C/W only when the E-pad is properly attached. Failure to do so risks exceeding the 155°C thermal shutdown threshold under 800mA load, especially in enclosed or still-air environments.
ISL9305IRTBFNCZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 16-WQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- 1.5V, 800mA
- Voltage/Current - Output 2:
- 2.5V, 800mA
- Voltage/Current - Output 3:
- 3.3V, 350mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TQFN (4x4)
ISL9305IRTBFNCZ-T FAQ
1.How can I place an order for ISL9305IRTBFNCZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL9305IRTBFNCZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL9305IRTBFNCZ-T reliable?
The price and inventory of ISL9305IRTBFNCZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL9305IRTBFNCZ-T is usually 5 days.
3.What payment methods are accepted for ISL9305IRTBFNCZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL9305IRTBFNCZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL9305IRTBFNCZ-T?
ISL9305IRTBFNCZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL9305IRTBFNCZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL9305IRTBFNCZ-T?
For technical support, including ISL9305IRTBFNCZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL9305IRTBFNCZ-T requirements.
6.How does Aetrix verify that ISL9305IRTBFNCZ-T is sourced from the original manufacturer or authorized distributors?
All ISL9305IRTBFNCZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL9305IRTBFNCZ-T meets industry standards.
7.What is the process for return or replacement of ISL9305IRTBFNCZ-T?
All ISL9305IRTBFNCZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL9305IRTBFNCZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL9305IRTBFNCZ-T part is unused and in its original packaging.
Return procedure for ISL9305IRTBFNCZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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