Renesas ISL9305IRTHWBNLZ-T
- Part No.:
- ISL9305IRTHWBNLZ-T
- Manufacturer:
- Renesas
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-WQFN Exposed Pad
- Datasheet:
-
ISL9305IRTHWBNLZ-T.pdf
- Description:
- IC REG QUAD BUCK/LNR 3MHZ 16TQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL9305IRTHWBNLZ-T from Renesas (formerly Intersil) is a dual-buck + dual-LDO mini-PMIC for single-cell Li-ion/Li-polymer battery-powered systems. It integrates two 3MHz, 1.5A synchronous step-down converters (DCD1 = 1.2V, DCD2 = 1.5V) and two 300mA LDOs (LDO1 = 3.3V, LDO2 = 2.9V), all I²C-programmable with on-the-fly voltage slew control - used in smartphone application processors and DSP core power rails.
For engineers reviewing the ISL9305IRTHWBNLZ-T datasheet, ISL9305IRTHWBNLZ-T pinout, ISL9305IRTHWBNLZ-T application, or ISL9305IRTHWBNLZ-T equivalent, key selection considerations include factory-fixed output voltages, 400kb/s I²C interface timing, 16-pin 4mm×4mm TQFN package thermal performance, and integrated power-good monitoring with programmable 1–200ms delay.
Technical Context
The ISL9305IRTHWBNLZ-T implements peak-current-mode PWM control for both buck converters, enabling fast transient response and pulse-by-pulse current limiting. Each converter supports skip mode (PFM) under light load and forced PWM mode via I²C register programming (DCD_PARAMETER[1:0]), with active output discharge enabled by default using an internal 115Ω bleeding resistor.
Its dual LDOs operate from 1.5V–5.5V input and deliver fixed outputs (3.3V/2.9V) with dropout as low as 80mV at 300mA for VO > 2.8V. The open-drain DCDPG pin monitors combined DCD1/DCD2 power-good status with user-selectable delay (1/50/150/200ms) programmed via SYS_PARAMETER[5:4].
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| DCD1 Output Voltage | Factory-fixed 1.2V - eliminates external feedback resistors and reduces BOM count for stable core rail. |
| DCD2 Output Voltage | Factory-fixed 1.5V - provides dedicated I/O or memory rail without layout-sensitive resistor networks. |
| LDO1 / LDO2 Outputs | Fixed 3.3V / 2.9V - enables immediate use in analog/audio subsystems without I²C initialization overhead. |
| Switching Frequency | 3.0MHz ±0.4MHz - permits use of 1.5µH inductors and compact 0603/0805 ceramic capacitors. |
| I²C Interface Speed | 400kb/s - supports real-time dynamic voltage scaling (DVS) during processor state transitions. |
| Quiescent Current (All Enabled) | 100–130µA typical - extends battery runtime in always-on system standby modes. |
| Thermal Shutdown Threshold | 155°C with 30°C hysteresis - protects against sustained overload or poor PCB heatsinking. |
Pinout & Package
ISL9305IRTHWBNLZ-T is housed in a thermally enhanced 16-lead 4mm × 4mm TQFN package with exposed E-pad (L16.4x4G). The E-pad must be soldered to system ground for optimal thermal dissipation and noise immunity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VINDCD1 (Pin 1) | Main input supply for DCD1 and internal logic | Accepts 2.5–5.5V; powers entire IC - requires local 10µF input capacitance. |
| FB1 (Pin 2) | DCD1 feedback node | Internally connected to 1.2V reference; shorted to VOLDO1 in fixed-output version - no external divider needed. |
| SCLK (Pin 3) | I²C clock input | 400kb/s compliant; requires external pull-up to VDDIO (1.8–3.6V). |
| SDAT (Pin 4) | I²C data bidirectional line | Open-drain; shares same pull-up as SCLK - supports multi-drop bus topology. |
| VINLDO1 (Pin 5) | LDO1 input supply | 1.5–5.5V range; may be sourced from DCD1, DCD2, or battery directly. |
| VOLDO1 (Pin 6) | LDO1 regulated output | Fixed 3.3V @ 300mA - low-noise (45µVRMS) for RF/analog circuitry. |
| VOLDO2 (Pin 7) | LDO2 regulated output | Fixed 2.9V @ 300mA - optimized for camera sensor or audio codec bias rails. |
| VINLDO2 (Pin 8) | LDO2 input supply | Independent input path allows flexible power sequencing vs. LDO1. |
| GNDLDO (Pin 9) | Power ground for both LDOs | Separate from buck grounds - minimizes switching noise coupling into LDO outputs. |
| DCDPG (Pin 10) | Open-drain DCD power-good indicator | Asserts high after programmable delay when both DCD outputs are within ±3% of nominal. |
| FB2 (Pin 11) | DCD2 feedback node | Internally tied to 1.5V reference - no external components required. |
| VINDCD2 (Pin 12) | Input supply for DCD2 | 2.5V to VINDCD1 - supports independent input sourcing (e.g., separate battery tap). |
| SW2 (Pin 13) | DCD2 switching node | Connects to inductor L2 - requires low-inductance layout and Kelvin grounding. |
| GNDDCD2 (Pin 14) | Power ground for DCD2 | Must be routed separately from GNDDCD1 and GNDLDO to avoid ground bounce. |
| GNDDCD1 (Pin 15) | Power ground for DCD1 | Dedicated return path for high-frequency buck current - critical for EMI control. |
| SW1 (Pin 16) | DCD1 switching node | Connects to inductor L1 - forms high-side switch node with P-MOSFET (RDS(on) = 0.14Ω typ). |
Key Features
| Feature | Design Value |
|---|---|
| Dual 1.5A buck converters with 3MHz switching | Enables <1mm² total passive area per channel - ideal for space-constrained mobile PCBs. |
| Factory-fixed DCD/LDO outputs | Eliminates 4 external feedback resistors and associated layout sensitivity - improves yield and test repeatability. |
| I²C-programmable slew rate (0.225–28.8mV/µs) | Prevents overshoot/undershoot during dynamic voltage scaling - avoids processor brown-out or latch-up. |
| Programmable DCDPG delay (1/50/150/200ms) | Aligns power-good assertion with system boot sequence timing - prevents premature firmware execution. |
| Active output discharge (115Ω internal bleed) | Ensures rapid output collapse (<1ms) when disabled - meets strict power-domain isolation requirements. |
| Separate LDO and buck ground pins | Reduces conducted noise coupling from switching nodes into sensitive analog rails - improves SNR in audio paths. |
Applications
| Smartphone Application Processor Core | Mobile Camera Module Power |
|---|---|
Use Scenario: Powers ARM Cortex-A series CPU cores requiring tightly regulated 1.2V supply with dynamic voltage/frequency scaling (DVFS). IC Role / Device Role / Timing Role: Primary core PMIC delivering DCD1 (1.2V/1.5A) with I²C-controlled slew rate and soft-start to meet SoC reset timing. Use Value: Factory-fixed 1.2V eliminates calibration drift; 3MHz switching enables ultra-compact 1.5µH inductors and reduces board area by >35% vs. 1MHz alternatives. | Use Scenario: Supplies image signal processor (ISP) and CMOS sensor analog/digital rails in dual-camera smartphones. IC Role / Device Role / Timing Role: Provides LDO1 (3.3V) for sensor I/O and LDO2 (2.9V) for analog front-end - sequenced via I²C enable bits. Use Value: Low 45µVRMS noise ensures clean pixel data; independent VINLDO1/VINLDO2 inputs allow flexible sourcing from DCD1 or battery. |
| Portable Media Player DSP Subsystem | Li-ion-Powered Industrial Handheld |
Use Scenario: Powers TI C5000 or Analog Devices SHARC DSP cores needing 1.5V I/O and 1.2V core rails with low quiescent current. IC Role / Device Role / Timing Role: Delivers DCD2 (1.5V/1.5A) for DSP I/O and DCD1 (1.2V/1.5A) for core - coordinated startup via DCDPG. Use Value: Skip mode achieves >85% efficiency at 10mA load - extends playback time in low-power decode states. | Use Scenario: Powers microcontroller, display driver, and wireless transceiver in ruggedized handheld test equipment. IC Role / Device Role / Timing Role: Dual buck converters supply MCU core (1.2V) and peripherals (1.5V); LDOs power RS-485 transceiver (3.3V) and BLE radio (2.9V). Use Value: 2.5–5.5V DCD input range accommodates full Li-ion discharge curve (4.2V → 2.8V); thermal shutdown protects during extended field operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-buck + dual-LDO PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | 3-channel buck + 2-channel LDO; 2.25MHz switching; no I²C slew rate control; different pinout and register map. | Targeted at OMAP3-based designs; lacks programmable DCDPG delay and active discharge. | Select when existing TPS65023 layout reuse is prioritized over dynamic voltage ramp control. |
| RT8070ZSP | Dual 2A buck only (no integrated LDOs); 3MHz switching; I²C interface with voltage/slew control; requires external LDOs for auxiliary rails. | Used where higher current capability (>1.5A) is needed and board space allows discrete LDO placement. | Select when LDO current >300mA or independent LDO input flexibility outweighs integration benefit. |
Compared with TPS65023RSBR and RT8070ZSP, the ISL9305IRTHWBNLZ-T uniquely combines factory-fixed dual-buck outputs, dual fixed LDOs, I²C slew control, and programmable DCDPG delay in a single 4mm×4mm package - reducing component count and layout complexity for cost-sensitive mobile applications.
Availability
ISL9305IRTHWBNLZ-T is available at Aetrix Electronics and suitable for smartphone application processor core power, mobile camera module power, portable media player DSP subsystems, and Li-ion-powered industrial handhelds requiring stable component supply across production lifecycles.
Supply support for ISL9305IRTHWBNLZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded design innovation, with origins in Intersil's precision analog and power management expertise.
The ISL9305H product line was designed specifically for space- and efficiency-critical battery-powered mobile devices, integrating multiple DC/DC and LDO functions with digital configurability to replace discrete power solutions in smartphones and portable instruments.
FAQ
What are the factory-programmed output voltages of the ISL9305IRTHWBNLZ-T?
The ISL9305IRTHWBNLZ-T has factory-fixed outputs: DCD1 = 1.2V, DCD2 = 1.5V, LDO1 = 3.3V, and LDO2 = 2.9V. These values are laser-trimmed during manufacturing and require no external feedback resistors. The ISL9305IRTHWBNLZ-T supports I²C reprogramming of all four outputs within defined ranges (e.g., DCD1 from 0.825V–3.6V), but defaults to these fixed values at power-up unless modified via register writes.
Does the ISL9305IRTHWBNLZ-T support independent enable/disable control of each regulator?
Yes, the ISL9305IRTHWBNLZ-T provides individual I²C control bits for enabling or disabling each regulator. Bits B0–B3 of the SYS_PARAMETER register (address 0x05h) control DCD1_EN, DCD2_EN, LDO1_EN, and LDO2_EN respectively. This allows precise power sequencing - for example, enabling LDO2 before DCD1 to power auxiliary circuitry prior to core domain activation - without requiring external GPIOs.
What is the purpose of the DCDPG pin on the ISL9305IRTHWBNLZ-T, and how is its delay configured?
The DCDPG pin on the ISL9305IRTHWBNLZ-T is an open-drain power-good indicator for the DCD1 and DCD2 outputs. Its assertion delay is configured via bits B5–B4 of the SYS_PARAMETER register (00 = 1ms, 01 = 50ms, 10 = 150ms, 11 = 200ms). When both DCDs are enabled and within ±3% of their nominal voltages, DCDPG releases after the selected delay to be pulled high externally - signaling system readiness to firmware.
Can the ISL9305IRTHWBNLZ-T operate with only one buck converter enabled?
Yes, the ISL9305IRTHWBNLZ-T fully supports single-buck operation. When only DCD1 or DCD2 is enabled (via SYS_PARAMETER bits), the DCDPG pin reflects only that active converter's status. The unused converter's feedback pins (FB1/FB2) must still be connected per datasheet guidance - for fixed-output versions, FB1 and FB2 are internally tied to their respective outputs and require no external components.
How does the ISL9305IRTHWBNLZ-T handle thermal overload conditions?
The ISL9305IRTHWBNLZ-T incorporates thermal shutdown protection with a junction threshold of +155°C and hysteresis of +30°C (typical). When die temperature reaches 155°C, all regulators shut down immediately. Operation resumes only after temperature falls to ~125°C, beginning with soft-start to prevent inrush current. This behavior is intrinsic to the ISL9305IRTHWBNLZ-T silicon and requires no external circuitry or I²C intervention.
ISL9305IRTHWBNLZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 16-WQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- 1.2V, 1.5A
- Voltage/Current - Output 2:
- 1.5V, 1.5A
- Voltage/Current - Output 3:
- 3.3V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TQFN (4x4)
ISL9305IRTHWBNLZ-T FAQ
1.How can I place an order for ISL9305IRTHWBNLZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL9305IRTHWBNLZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL9305IRTHWBNLZ-T reliable?
The price and inventory of ISL9305IRTHWBNLZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL9305IRTHWBNLZ-T is usually 5 days.
3.What payment methods are accepted for ISL9305IRTHWBNLZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL9305IRTHWBNLZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL9305IRTHWBNLZ-T?
ISL9305IRTHWBNLZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL9305IRTHWBNLZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL9305IRTHWBNLZ-T?
For technical support, including ISL9305IRTHWBNLZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL9305IRTHWBNLZ-T requirements.
6.How does Aetrix verify that ISL9305IRTHWBNLZ-T is sourced from the original manufacturer or authorized distributors?
All ISL9305IRTHWBNLZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL9305IRTHWBNLZ-T meets industry standards.
7.What is the process for return or replacement of ISL9305IRTHWBNLZ-T?
All ISL9305IRTHWBNLZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL9305IRTHWBNLZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL9305IRTHWBNLZ-T part is unused and in its original packaging.
Return procedure for ISL9305IRTHWBNLZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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