Renesas ISL9305IRTHWCNYZ-T7A
- Part No.:
- ISL9305IRTHWCNYZ-T7A
- Manufacturer:
- Renesas
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-WQFN Exposed Pad
- Datasheet:
-
ISL9305IRTHWCNYZ-T7A.pdf
- Description:
- IC REG QUAD BUCK/LNR 3MHZ 16TQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,365
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Product details
Overview
ISL9305IRTHWCNYZ-T7A from Renesas Electronics is a dual-buck + dual-LDO mini-PMIC for Li-ion/Li-Polymer battery-powered systems. It integrates two 3MHz, 800mA synchronous step-down converters (DCD1/DCD2) with I²C-programmable output voltages (0.825V–3.6V at 25mV/step), and two 300mA low-dropout LDOs (LDO1/LDO2) with factory-fixed outputs of 3.3V and 0.9V respectively. It delivers power to DSP cores and application processors in smartphones.
For engineers reviewing the ISL9305IRTHWCNYZ-T7A datasheet, ISL9305IRTHWCNYZ-T7A pinout, ISL9305IRTHWCNYZ-T7A application, or ISL9305IRTHWCNYZ-T7A equivalent, key selection considerations include its 4mm×4mm TQFN-16 package, I²C-controlled slew rate (0.225–28.8 mV/µs), skip-mode efficiency optimization, dual PGOOD monitoring, and fixed LDO outputs enabling simplified biasing for memory I/O and low-voltage logic rails.
Technical Context
The ISL9305IRTHWCNYZ-T7A implements peak-current-mode PWM control for fast transient response in both DCD1 and DCD2, with programmable forced-PWM or skip-mode operation per converter. Its I²C interface supports 400 kbps transfers and enables on-the-fly voltage slewing, delay-programmable DCDPG assertion (1–200 ms), and independent enable/disable of all four regulators.
Each buck converter features internal P/N-MOSFETs (RDS(on) = 0.14 Ω / 0.11 Ω typ at VIN = 3.6V), 100% duty-cycle low-dropout mode, and active output discharge via a 115 Ω internal bleeding resistor. The LDOs operate across 1.5V–5.5V input and deliver ≤250 mV dropout at 300 mA for VO ≤ 2.1 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range (DCD) | 2.3V to 5.5V - supports single-cell Li-ion (2.7–4.2V) with margin for cold start and overvoltage transients |
| Switching Frequency | 2.6–3.4 MHz (typ 3 MHz) - enables use of 1.5 µH inductors and compact 0603/0805 ceramic capacitors |
| DCD Output Current | Up to 800 mA per channel - sufficient for ARM Cortex-A/M cores and GPU subsystems |
| LDO Output Current | 300 mA per channel - powers DDR I/O, sensor interfaces, or low-noise analog circuitry |
| I²C Interface Speed | 400 kbps - compatible with standard Fast-mode I²C controllers without timing redesign |
| Quiescent Current (Skip Mode) | 50 µA typ with both DCDs enabled - extends battery runtime in standby/sleep states |
| Package | 4 mm × 4 mm, 16-pin TQFN with exposed thermal pad - supports high-density mobile PCB layouts and efficient heat dissipation |
Pinout & Package
ISL9305IRTHWCNYZ-T7A is housed in a 4 mm × 4 mm, 16-lead TQFN package with an exposed thermal pad (E-pad) that must be soldered to system ground for thermal performance and EMI reduction.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VINDCD1 | Main input supply for DCD1 and internal circuitry | Primary power rail; also powers digital/analog blocks - requires local 10 µF input capacitance |
| FB1 | Feedback node for DCD1 output regulation | Connected directly to DCD1 output (fixed version); sets 0.8V reference point for adjustable configurations |
| SCLK | I²C clock input | Requires external pull-up; supports 400 kbps timing - must be routed away from SW nodes |
| SDAT | I²C data bidirectional line | Open-drain; shares pull-up with SCLK - enables register read/write and dynamic voltage scaling |
| VINLDO1 / VINLDO2 | Independent input supplies for LDO1 and LDO2 | Can be sourced from battery or DCD outputs - decoupling required per LDO input |
| VOLDO1 / VOLDO2 | Fixed-output LDO terminals | Factory-set to 3.3V and 0.9V respectively - no external feedback needed; each requires local 1 µF output cap |
| DCDPG | Open-drain power-good monitor for DCD1/DCD2 | Asserts after programmable 1–200 ms delay when both outputs are within ±3% of nominal - used for system sequencing |
| SW1 / SW2 | Switching node outputs for DCD1/DCD2 | Connect to inductor high-side; highly noisy - must be short, wide, and isolated from sensitive traces |
| GNDDCD1 / GNDDCD2 / GNDLDO | Separate power grounds | Minimizes coupling between switching and linear sections - tied together only at single-point E-pad |
Key Features
| Feature | Design Value |
|---|---|
| Dual 3 MHz synchronous buck converters | Enables ultra-compact DC/DC stage using 1.5 µH inductors and 4.7 µF output caps - reduces board area by >40% vs. 500 kHz designs |
| I²C-programmable slew rate (0.225–28.8 mV/µs) | Prevents overshoot/undershoot during dynamic voltage scaling for CPU frequency transitions - eliminates need for external slew control circuitry |
| Independent skip-mode or forced-PWM selection per buck | Optimizes light-load efficiency (e.g., display backlight off) while maintaining low noise during audio playback or RF transmission |
| Active output discharge (115 Ω internal bleed) | Ensures rapid, controlled discharge of DCD outputs upon disable - prevents floating rails and improves system reset reliability |
| Programmable DCDPG delay (1–200 ms) | Aligns power-good assertion with downstream LDO startup or FPGA configuration timing - eliminates external RC timing networks |
Applications
| Smartphone Application Processor Core | Mobile DDR Memory I/O Supply |
|---|---|
Use Scenario: Powers ARM Cortex-A series CPU cores requiring dynamically scaled voltage (e.g., 0.9V–1.2V) based on workload. IC Role / Device Role / Timing Role: Dual-buck regulator delivering precise, I²C-adjustable VDD_CPU and VDD_GPU rails with synchronized soft-start and PGOOD sequencing. Use Value: Enables real-time DVFS with <1.5% output accuracy and 28.8 mV/µs slew control - meets ARM TRM timing margins for frequency transitions. | Use Scenario: Supplies 3.3V I/O voltage to LPDDR2/LPDDR3 memory interfaces in handheld devices. IC Role / Device Role / Timing Role: LDO1 provides low-noise, high-PSRR (55 dB @ 1 kHz) 3.3V rail decoupled from noisy switching converters. Use Value: Maintains signal integrity during high-speed memory bursts - 45 µVRMS output noise avoids bit errors in 400+ Mbps data lanes. |
| Low-Voltage Sensor Subsystem | Always-On Microcontroller Bias Rail |
Use Scenario: Powers MEMS accelerometers, ambient light sensors, and touch controllers operating at 0.9V. IC Role / Device Role / Timing Role: LDO2 delivers factory-fixed 0.9V output with 125 mV dropout at 300 mA - optimized for ultra-low-power wake-on-motion functions. Use Value: Achieves 20 µA typical quiescent current per enabled LDO - extends coin-cell or backup battery life beyond 1 year. | Use Scenario: Supplies always-on domain for real-time clocks, interrupt controllers, and secure boot logic in sleep mode. IC Role / Device Role / Timing Role: DCD2 configured in skip mode provides 1.8V rail with 50 µA total IQ - maintains regulation during multi-day deep-sleep cycles. Use Value: Reduces system-wide leakage by >65% vs. fixed-frequency operation - critical for IoT endpoint energy budgets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-buck + dual-LDO PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65910A3RSLR | 12-bit I²C voltage resolution (12.5 mV/step), integrated RTC, but larger 5×5 mm QFN-48 package and no active discharge | Targets industrial tablets with longer design cycles; lacks 0.9V factory-fixed LDO for ultra-low-V logic | Select if RTC integration and finer voltage granularity outweigh size and discharge requirements |
| RT8070ZSP | Single 2A buck + dual 300mA LDOs; no I²C interface - uses external resistors for fixed outputs | Suitable for cost-sensitive feature phones; cannot support dynamic voltage scaling or sequencing control | Select only for static-rail applications where firmware-based voltage control is unnecessary |
Compared with TPS65910A3RSLR and RT8070ZSP, ISL9305IRTHWCNYZ-T7A uniquely combines factory-fixed 0.9V/3.3V LDOs, 3 MHz switching, and I²C slew-rate control in a 4×4 mm footprint - making it optimal for space-constrained, battery-life-critical smartphone SoC power delivery.
Availability
ISL9305IRTHWCNYZ-T7A is available at Aetrix Electronics and suitable for smartphone application processor core supplies, mobile DDR memory I/O rails, low-voltage sensor subsystems, and always-on microcontroller bias rails requiring stable component supply across high-volume production ramps.
Supply support for ISL9305IRTHWCNYZ-T7A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded design innovation for automotive, industrial, infrastructure, and IoT applications.
The ISL9305IRTHWCNYZ-T7A belongs to Renesas' mini-PMIC product line, engineered specifically for compact, battery-powered portable electronics requiring tightly regulated, dynamically scalable multi-rail power with minimal external components.
FAQ
What are the factory-programmed output voltages for ISL9305IRTHWCNYZ-T7A?
The ISL9305IRTHWCNYZ-T7A has factory-fixed LDO outputs: LDO1 = 3.3V and LDO2 = 0.9V. Its DCD1 and DCD2 buck converters are preset to 1.2V and 1.8V respectively, as indicated by the "WC" and "NY" codes in the part marking "9305I WCNYZ". These values are confirmed in the Ordering Information table on page 4 of FN7605 Rev 2.00.
Does ISL9305IRTHWCNYZ-T7A support independent enable/disable of each regulator via I²C?
Yes, ISL9305IRTHWCNYZ-T7A supports full independent control: bits B0–B3 of the SYS_PARAMETER register (0x05h) allow individual enable/disable of DCD1, DCD2, LDO1, and LDO2. This enables flexible power sequencing - for example, powering up LDO2 (0.9V) before DCD1 (1.2V) to meet SoC boot requirements - without modifying hardware.
What is the maximum allowable input voltage on the SW1 and SW2 pins of ISL9305IRTHWCNYZ-T7A?
The absolute maximum rating for SW1 and SW2 pins is −1.5V to +6.5V relative to ground, as specified on page 5 of FN7605 Rev 2.00. This accommodates inductive kickback during switch turn-off and ensures robustness against layout-induced ringing, provided proper snubbing and layout practices (short/wide traces, minimized loop area) are followed.
Can ISL9305IRTHWCNYZ-T7A operate with only one buck converter enabled while the other is disabled?
Yes, ISL9305IRTHWCNYZ-T7A fully supports asymmetric operation. When only DCD1 is enabled, the DCDPG pin reflects only DCD1's power-good status. The disabled DCD2 enters low-quiescent state (<5 µA) and its SW2 node is actively discharged via the internal 115 Ω resistor - preventing floating conditions and ensuring clean rail shutdown per JEDEC JESD78 latch-up immunity requirements.
What thermal derating applies to ISL9305IRTHWCNYZ-T7A at 85°C ambient?
At +85°C ambient, ISL9305IRTHWCNYZ-T7A maintains full 800 mA per buck and 300 mA per LDO capability when the PCB includes the recommended thermal pad (9 vias to solid ground plane) and θJA remains ≤40.2°C/W. Thermal shutdown activates at +155°C junction temperature with +30°C hysteresis, allowing safe recovery at +130°C - verified per JEDEC JESD51-1 test conditions.
ISL9305IRTHWCNYZ-T7A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 16-WQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- 1.2V, 1.5A
- Voltage/Current - Output 2:
- 1.8V, 1.5A
- Voltage/Current - Output 3:
- 3.3V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TQFN (4x4)
ISL9305IRTHWCNYZ-T7A FAQ
1.How can I place an order for ISL9305IRTHWCNYZ-T7A through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL9305IRTHWCNYZ-T7A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL9305IRTHWCNYZ-T7A reliable?
The price and inventory of ISL9305IRTHWCNYZ-T7A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL9305IRTHWCNYZ-T7A is usually 5 days.
3.What payment methods are accepted for ISL9305IRTHWCNYZ-T7A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL9305IRTHWCNYZ-T7A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL9305IRTHWCNYZ-T7A?
ISL9305IRTHWCNYZ-T7A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL9305IRTHWCNYZ-T7A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL9305IRTHWCNYZ-T7A?
For technical support, including ISL9305IRTHWCNYZ-T7A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL9305IRTHWCNYZ-T7A requirements.
6.How does Aetrix verify that ISL9305IRTHWCNYZ-T7A is sourced from the original manufacturer or authorized distributors?
All ISL9305IRTHWCNYZ-T7A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL9305IRTHWCNYZ-T7A meets industry standards.
7.What is the process for return or replacement of ISL9305IRTHWCNYZ-T7A?
All ISL9305IRTHWCNYZ-T7A units undergo pre-shipment inspection (PSI). If there is an issue with ISL9305IRTHWCNYZ-T7A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL9305IRTHWCNYZ-T7A part is unused and in its original packaging.
Return procedure for ISL9305IRTHWCNYZ-T7A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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