Renesas ISL9305IRTWCLBZ-T
- Part No.:
- ISL9305IRTWCLBZ-T
- Manufacturer:
- Renesas
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-WQFN Exposed Pad
- Datasheet:
-
ISL9305IRTWCLBZ-T.pdf
- Description:
- IC REG QUAD BUCK/LNR 3MHZ 16TQFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,404
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Product details
Overview
ISL9305IRTWCLBZ-T from Renesas Electronics is a dual-output PMIC integrating two 3MHz synchronous step-down converters (800mA each) and two low-input LDOs (300mA each), with I²C programmability for dynamic voltage scaling in battery-powered microprocessor systems. It supports 2.3V–5.5V input, delivers factory pre-set DCD1/DCD2 outputs of 1.2V/1.8V and LDO1/LDO2 outputs of 2.9V/1.5V, and operates across –40°C to +85°C in a 4mm×4mm TQFN-16 package.
For engineers reviewing the ISL9305IRTWCLBZ-T datasheet, ISL9305IRTWCLBZ-T pinout, ISL9305IRTWCLBZ-T application, or ISL9305IRTWCLBZ-T equivalent, this page provides verified technical context, confirmed pin functions, real-world use cases in mobile SoC power domains, and validated alternative options for multi-rail Li-ion battery management.
Technical Context
The ISL9305IRTWCLBZ-T implements peak-current-mode PWM control for both buck converters, enabling fast transient response and pulse-by-pulse current limiting. Its 3MHz switching frequency allows compact 1.5µH inductors and low-ESR ceramic capacitors, while skip mode (PFM) operation under light load reduces quiescent current to 50µA typical.
I²C interface (400kb/s) enables on-the-fly output voltage slew rate control (0.225–28.8mV/µs), programmable power-good delay (1–200ms), and independent enable/disable of each regulator. The device features active output discharge (115Ω internal bleeding resistor), thermal shutdown at 155°C, and UVLO thresholds of 2.2V (DCD inputs) and 1.4V (LDO inputs).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range (DCD) | 2.3V to 5.5V - supports single-cell Li-ion/Li-Polymer battery input without external pre-regulation |
| DCD Output Current | 800mA per channel - sufficient for powering ARM Cortex-A cores or DSP subsystems |
| LDO Output Current | 300mA per channel - suitable for I/O rails, memory interfaces, or analog peripherals |
| Switching Frequency | 3.0MHz ±0.4MHz - enables use of 1.5µH inductors and minimizes solution footprint |
| I²C Interface Speed | 400kb/s - compatible with standard Fast-mode I²C controllers in application processors |
| Quiescent Current (Skip Mode) | 50µA typical - extends battery runtime during system idle or suspend states |
| Thermal Shutdown Threshold | 155°C with 30°C hysteresis - protects against sustained overload or poor PCB thermal design |
Pinout & Package
ISL9305IRTWCLBZ-T is housed in a thermally enhanced 4mm × 4mm, 16-lead TQFN package with exposed E-pad for improved heat dissipation. Pin numbering follows top-view orientation with pin 1 at top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VINDCD1 (Pin 1) | Main input supply for DCD1 and internal circuitry | Primary power rail for first buck converter; also powers digital/analog core circuits |
| FB1 (Pin 2) | Feedback node for DCD1 output regulation | Connects to voltage divider for adjustable versions; tied directly to VODCD1 for fixed-output variant ISL9305IRTWCLBZ-T |
| SCLK (Pin 3) | I²C clock input | Accepts standard I²C clock signals up to 400kHz; requires external pull-up resistor |
| SDAT (Pin 4) | I²C bidirectional data line | Open-drain interface for register read/write; shares pull-up with SCLK |
| VINLDO1 (Pin 5) | Input supply for LDO1 | Can be powered from battery or DCD1 output; supports 1.5V–5.5V range |
| VOLDO1 (Pin 6) | LDO1 regulated output | Factory pre-set to 2.9V; programmable via I²C in 50mV steps from 0.9V to 3.6V |
| VOLDO2 (Pin 7) | LDO2 regulated output | Factory pre-set to 1.5V; programmable via I²C in 50mV steps from 0.9V to 3.6V |
| VINLDO2 (Pin 8) | Input supply for LDO2 | Independent input path; supports same 1.5V–5.5V range as LDO1 |
| GNDLDO (Pin 9) | Power ground for both LDOs | Dedicated ground return to minimize noise coupling into sensitive analog outputs |
| DCDPG (Pin 10) | Open-drain power-good indicator | Signals combined status of DCD1/DCD2 outputs; programmable delay 1–200ms |
| FB2 (Pin 11) | Feedback node for DCD2 output regulation | Tied directly to VODCD2 for fixed-output ISL9305IRTWCLBZ-T |
| VINDCD2 (Pin 12) | Main input supply for DCD2 | May share VINDCD1 or use separate path; supports 2.3V–VINDCD1 range |
| SW2 (Pin 13) | DCD2 switching node | Connects to inductor; high di/dt node requiring short, wide trace routing |
| GNDDCD2 (Pin 14) | Power ground for DCD2 | Separate ground return for second buck converter to reduce cross-talk |
| GNDDCD1 (Pin 15) | Power ground for DCD1 | Isolated ground path improves stability and EMI performance |
| SW1 (Pin 16) | DCD1 switching node | Connects to inductor; must be routed away from feedback and analog traces |
Key Features
| Feature | Design Value |
|---|---|
| Dual 3MHz synchronous buck converters | Enables ultra-compact DC/DC solutions using 1.5µH inductors and <10µF ceramic output caps |
| I²C-programmable output voltages | Allows dynamic voltage scaling for CPU/GPU cores without hardware changes |
| Configurable skip mode or forced PWM | Optimizes efficiency across full load range: >85% at 1mA, >90% at 100mA, >92% at 500mA |
| Active output discharge (115Ω) | Ensures rapid, controlled discharge of DCD outputs during disable-critical for sequencing compliance |
| Programmable DCDPG delay (1–200ms) | Supports precise power-rail sequencing in multi-voltage SoC applications |
| Thermal-enhanced 4mm×4mm TQFN | θJA = 40.2°C/W enables >1.2W continuous power dissipation with minimal board area |
Applications
| Mobile Application Processor Core Power | Multi-Rail Portable Instrumentation |
|---|---|
Use Scenario: Powers ARM Cortex-A series CPU cores and GPU clusters in smartphones and tablets using single Li-ion battery input. IC Role / Device Role / Timing Role: Dual buck converters deliver 1.2V (DCD1) and 1.8V (DCD2); LDOs supply 2.9V I/O and 1.5V analog subsystems. Use Value: I²C programmability enables DVFS during workload transitions; 3MHz switching minimizes passive component count and PCB area. | Use Scenario: Supplies multiple precision analog and digital rails in handheld test equipment powered by rechargeable Li-Polymer cells. IC Role / Device Role / Timing Role: DCDs power FPGA fabric and ADC/DAC digital cores; LDOs provide clean 2.9V and 1.5V for sensor front-ends and reference buffers. Use Value: Low 45µVRMS LDO noise ensures signal integrity; independent enable/disable supports flexible power sequencing. |
| DSP Core and Memory Subsystem | Low-Power Wearable SoC Platform |
Use Scenario: Delivers tightly regulated voltages to TI C6000 or Analog Devices SHARC DSPs and associated DDR/LPDDR memory interfaces. IC Role / Device Role / Timing Role: DCD1 (1.2V) powers DSP core; DCD2 (1.8V) supplies memory I/O; LDOs feed PLLs and ADC references. Use Value: 1.5% output accuracy and 55dB PSRR ensure stable clock generation and low-jitter sampling. | Use Scenario: Manages power for Bluetooth LE SoCs and MEMS sensors in fitness trackers and smartwatches. IC Role / Device Role / Timing Role: DCDs supply processor and radio; LDOs deliver 2.9V to display driver and 1.5V to inertial measurement unit (IMU). Use Value: 50µA skip-mode IQ extends battery life beyond 7 days; small 4mm×4mm footprint fits constrained wearable layouts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Triple 600mA buck + dual LDO; 2.25MHz switching; no I²C slew rate control; different pinout | Requires layout change; lacks on-the-fly voltage ramp control needed for DVFS | Select when fixed-voltage sequencing suffices and I²C programmability is not required |
| MAX8646ETE+ | Dual 1A buck + triple LDO; 3MHz switching; I²C interface; 5mm×5mm TQFN-28 package | Larger footprint and higher pin count; supports higher current but less integration density | Choose for designs needing >800mA per buck or additional LDOs, accepting larger board area |
Compared with TPS65023RSBR and MAX8646ETE+, the ISL9305IRTWCLBZ-T offers superior integration density in a 4mm×4mm package, precise 25mV-step I²C voltage programming for dynamic power management, and lower quiescent current in skip mode-making it optimal for space-constrained, battery-sensitive mobile SoC applications.
Availability
ISL9305IRTWCLBZ-T is available at Aetrix Electronics and suitable for cellular phones, portable instrumentation, and wearable electronics requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for ISL9305IRTWCLBZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering microcontrollers, analog power, and SoC solutions for automotive, industrial, and consumer markets.
The ISL9305IRTWCLBZ-T belongs to Renesas' mini-PMIC product line, designed specifically for efficient, compact, and software-configurable power delivery in battery-powered mobile and portable electronics.
FAQ
What are the factory pre-set output voltages for ISL9305IRTWCLBZ-T?
The ISL9305IRTWCLBZ-T has factory pre-set outputs: DCD1 = 1.2V, DCD2 = 1.8V, LDO1 = 2.9V, and LDO2 = 1.5V. These values are fixed at manufacturing and can be modified via I²C commands to adjacent 25mV (buck) or 50mV (LDO) steps within their respective ranges. No external resistors are required for these default settings.
Does ISL9305IRTWCLBZ-T support independent enable/disable of each regulator?
Yes, ISL9305IRTWCLBZ-T supports full independent control via its I²C interface. Each of the four regulators-DCD1, DCD2, LDO1, and LDO2-has a dedicated enable bit in the SYS_PARAMETER register (0x05h). This allows precise power sequencing, dynamic rail activation/deactivation, and fault isolation without affecting other outputs.
What is the maximum supported I²C clock frequency for ISL9305IRTWCLBZ-T?
The ISL9305IRTWCLBZ-T supports standard Fast-mode I²C operation up to 400kb/s. Its SCLK and SDAT pins meet I²C bus electrical specifications, including open-drain drive strength and timing margins. Pull-up resistors must be selected based on bus capacitance and host controller voltage, with recommended values between 2.2kΩ and 10kΩ.
How does the DCDPG pin function on ISL9305IRTWCLBZ-T?
The DCDPG pin on ISL9305IRTWCLBZ-T is an open-drain output indicating combined power-good status of DCD1 and DCD2. When both are enabled and within ±3% of nominal voltage, DCDPG releases after a programmable 1–200ms delay to be pulled high externally. If either output falls outside regulation, DCDPG pulls low. It reflects only active converters-disabled channels do not affect its state.
Can ISL9305IRTWCLBZ-T operate with a 2.3V input supply?
Yes, ISL9305IRTWCLBZ-T supports a minimum input voltage of 2.3V for its DCD converters, matching the lower limit of a depleted single-cell Li-ion battery. At this voltage, DCD1 (1.2V) and DCD2 (1.8V) remain functional in 100% duty-cycle dropout mode, with P-channel MOSFET RDS(on) of 0.24Ω (typ) ensuring minimal voltage loss under 800mA load.
ISL9305IRTWCLBZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 16-WQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- 1.2V, 800mA
- Voltage/Current - Output 2:
- 1.8V, 800mA
- Voltage/Current - Output 3:
- 2.9V, 350mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TQFN (4x4)
ISL9305IRTWCLBZ-T FAQ
1.How can I place an order for ISL9305IRTWCLBZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL9305IRTWCLBZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL9305IRTWCLBZ-T reliable?
The price and inventory of ISL9305IRTWCLBZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL9305IRTWCLBZ-T is usually 5 days.
3.What payment methods are accepted for ISL9305IRTWCLBZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL9305IRTWCLBZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL9305IRTWCLBZ-T?
ISL9305IRTWCLBZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL9305IRTWCLBZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL9305IRTWCLBZ-T?
For technical support, including ISL9305IRTWCLBZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL9305IRTWCLBZ-T requirements.
6.How does Aetrix verify that ISL9305IRTWCLBZ-T is sourced from the original manufacturer or authorized distributors?
All ISL9305IRTWCLBZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL9305IRTWCLBZ-T meets industry standards.
7.What is the process for return or replacement of ISL9305IRTWCLBZ-T?
All ISL9305IRTWCLBZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL9305IRTWCLBZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL9305IRTWCLBZ-T part is unused and in its original packaging.
Return procedure for ISL9305IRTWCLBZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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