Renesas ISL9305IRTWCNLZ-T
- Part No.:
- ISL9305IRTWCNLZ-T
- Manufacturer:
- Renesas
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-WQFN Exposed Pad
- Datasheet:
-
ISL9305IRTWCNLZ-T.pdf
- Description:
- IC REG QUAD BUCK/LNR 3MHZ 16TQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL9305IRTWCNLZ-T from Renesas Electronics is a mini-PMIC integrating two 3MHz synchronous step-down converters (800mA each) and two low-input LDOs (300mA each), with I²C programmability for dynamic voltage scaling in battery-powered microprocessor systems. It supports 2.3V–5.5V input, delivers factory pre-set DCD1/DCD2 outputs of 1.2V/1.8V and LDO1/LDO2 outputs of 3.3V/2.9V, and operates across –40°C to +85°C.
For engineers reviewing the ISL9305IRTWCNLZ-T datasheet, ISL9305IRTWCNLZ-T pinout, ISL9305IRTWCNLZ-T application, or ISL9305IRTWCNLZ-T equivalent, key selection considerations include I²C-controlled slew rate (0.225–28.8 mV/µs), skip-mode efficiency optimization, PGOOD delay programming (1–200 ms), and dual-buck + dual-LDO integration for multi-rail mobile SoC power delivery.
Technical Context
The ISL9305IRTWCNLZ-T implements peak-current-mode PWM control for both buck converters, enabling fast transient response and pulse-by-pulse current limiting. Its 3MHz switching frequency permits ultra-small external magnetics (e.g., 1.5µH inductors), while skip mode (PFM) reduces quiescent current to 50µA typ under light load.
I²C interface (400kb/s) enables on-the-fly output voltage adjustment at 25mV/step for DCDs and 50mV/step for LDOs, plus configuration of forced PWM vs. auto-skip mode, phase alignment, active discharge, and programmable PGOOD delay-critical for coordinated rail sequencing in DSP core and memory subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range (DCD) | 2.3V to 5.5V - supports single Li-ion/Li-Polymer battery input without pre-regulation |
| DCD Output Current | 800mA per channel - sufficient for ARM Cortex-A/M cores and LPDDR interfaces |
| LDO Output Current | 300mA per channel - powers low-noise analog blocks or I/O rails requiring PSRR >55dB |
| Switching Frequency | 2.6–3.4MHz (typ 3MHz) - enables compact 0603/0805 passive footprint and reduced EMI filtering |
| I²C Interface Speed | 400kb/s - compatible with standard Fast-mode I²C controllers in application processors |
| Quiescent Current (Skip Mode) | 50µA typ (both DCDs enabled) - extends battery runtime in standby/sleep states |
| PGOOD Delay Range | 1ms to 200ms - configurable via register for precise power-rail sequencing timing |
Pinout & Package
ISL9305IRTWCNLZ-T uses a thermally enhanced 4mm × 4mm, 16-lead TQFN package with exposed E-pad for PCB heat dissipation. Pin assignments are validated per FN7605 Rev 2.00, Page 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VINDCD1 | Main input supply for DCD1 and internal circuitry | Primary power source for first buck converter and digital/analog core; must be decoupled with ≥10µF ceramic capacitor |
| FB1 | Feedback node for DCD1 output regulation | Connects to voltage divider for adjustable versions; tied directly to VODCD1 for fixed-output variants like ISL9305IRTWCNLZ-T |
| SCLK | I²C clock input | Requires external pull-up resistor; timing compliant with Fast-mode I²C (400kb/s max) |
| SDAT | I²C bidirectional data line | Open-drain structure; shares same pull-up as SCLK; supports read/write and auto-increment register access |
| VINLDO1 / VINLDO2 | Input supplies for LDO1 and LDO2 | Accept 1.5V–5.5V; may be fed from DCD outputs or battery; UVLO threshold ~1.4V |
| VOLDO1 / VOLDO2 | Regulated LDO outputs | Factory pre-set to 3.3V and 2.9V respectively; programmable in 50mV steps via I²C registers 0x02/0x03 |
| DCDPG | Open-drain power-good indicator | Asserts high after programmable delay when both DCD outputs are within ±3% of nominal; sinks ≥1mA |
| SW1 / SW2 | Switching nodes for DCD1/DCD2 | Connect to inductor terminals; high di/dt nodes requiring short, wide traces and ground plane separation |
| GNDDCD1 / GNDDCD2 / GNDLDO | Power grounds | Separate ground returns minimize noise coupling between switching and linear regulators; all tied to E-pad |
Key Features
| Feature | Design Value |
|---|---|
| Dual 3MHz synchronous buck converters | Enables use of 1.5µH inductors and 4.7µF output caps-reducing solution size by >40% vs. 1MHz designs |
| I²C-programmable slew rate (0.225–28.8 mV/µs) | Allows controlled voltage ramping during DVFS transitions to prevent undershoot/overshoot on sensitive SoC rails |
| Configurable skip mode or forced PWM operation | Optimizes efficiency across load range: >85% at 1mA, >90% at 100mA, maintaining low noise in forced PWM for RF sections |
| Active output discharge (115Ω bleed resistor) | Ensures rapid, controlled discharge of DCD outputs upon disable-preventing floating voltages in power-down sequences |
| Programmable PGOOD delay (1–200 ms) | Supports staggered rail enable timing required for multi-voltage SoCs (e.g., core, memory, I/O) without external timers |
Applications
| Smartphone Application Processor Power | DSP Core & Memory Subsystem |
|---|---|
Use Scenario: Powers ARM-based application processor (e.g., Cortex-A7/A53) with independent core, GPU, and I/O voltage domains from a single Li-Po cell. IC Role / Device Role / Timing Role: Mini-PMIC provides four regulated rails (1.2V core, 1.8V GPU, 3.3V I/O, 2.9V memory interface) with synchronized startup and I²C-managed DVFS. Use Value: Eliminates need for discrete DC/DC + LDO combinations; reduces BOM count by 6+ components and PCB area by >30%. | Use Scenario: Supplies low-noise, tightly regulated voltages to a real-time DSP and its associated SRAM/SDRAM in portable medical instrumentation. IC Role / Device Role / Timing Role: Delivers 1.2V/1.8V buck outputs for digital logic and 3.3V/2.9V LDO outputs for analog front-end and memory I/O with >55dB PSRR at 1kHz. Use Value: Maintains signal integrity during high-speed data acquisition by isolating switching noise from analog sections via dedicated LDO paths. |
| Wearable Sensor Hub Power | Ultra-Low-Power IoT Node |
Use Scenario: Powers multi-sensor hub (accelerometer, gyroscope, environmental sensors) in compact wearable form factor with strict thermal and size constraints. IC Role / Device Role / Timing Role: Provides 1.2V system rail and 2.9V sensor interface rail; leverages skip mode to achieve 50µA quiescent current during motion-sensing sleep cycles. Use Value: Extends battery life to >7 days on coin-cell equivalent by minimizing no-load losses without sacrificing wake-up responsiveness. | Use Scenario: Enables energy harvesting-powered IoT endpoint with intermittent operation, requiring fast rail reactivation and precise brownout recovery. IC Role / Device Role / Timing Role: Integrates UVLO (2.2V DCD, 1.4V LDO), thermal shutdown (155°C), and programmable PGOOD to ensure deterministic power-up and fault-safe shutdown. Use Value: Guarantees reliable operation across variable input (2.3–5.5V) and ambient conditions (–40°C to +85°C) without external supervision circuitry. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Triple 600mA buck + dual 300mA LDO; I²C interface; 2.5–6V input; no programmable slew rate or PGOOD delay | Targets OMAP3/DM365 platforms; lacks fine-grained DVFS control needed for modern Cortex-A series | Choose if fixed 1.2V/1.3V/1.8V buck outputs and simpler I²C register map suffice; avoid when slew-controlled rail transitions are required |
| RT8059ZSP | Dual 800mA buck only (no integrated LDOs); 2.5–5.5V input; 3MHz switching; I²C programmable but no PGOOD or active discharge | Requires external LDOs for auxiliary rails; suitable where board space allows discrete regulation | Select when LDO requirements are minimal or handled separately; not viable for fully integrated quad-rail solutions like ISL9305IRTWCNLZ-T |
Compared with TPS65023RSBR and RT8059ZSP, the ISL9305IRTWCNLZ-T uniquely combines dual 800mA bucks, dual 300mA LDOs, I²C-programmable slew rate, and configurable PGOOD delay in a 4mm×4mm package-enabling compact, sequenced, and dynamically scalable power for next-generation mobile SoCs without design compromises.
Availability
ISL9305IRTWCNLZ-T is available at Aetrix Electronics and suitable for smartphone application processor power, DSP core & memory subsystems, wearable sensor hubs, and ultra-low-power IoT nodes requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for ISL9305IRTWCNLZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering microcontrollers, analog, power, and SoC products for automotive, industrial, infrastructure, and IoT markets.
The ISL9305IRTWCNLZ-T belongs to Renesas' mini-PMIC product line, engineered specifically for space-constrained, battery-powered mobile devices requiring highly integrated, I²C-configurable multi-rail power delivery with minimal external components.
FAQ
What are the factory pre-set output voltages for ISL9305IRTWCNLZ-T?
The ISL9305IRTWCNLZ-T has factory pre-set outputs of 1.2V for DCD1, 1.8V for DCD2, 3.3V for LDO1, and 2.9V for LDO2. These values are confirmed in the Ordering Information table (Page 4, FN7605 Rev 2.00) and cannot be altered by external resistors since it is a fixed-output variant. The I²C interface allows fine-tuning within ±25mV steps for DCDs and ±50mV steps for LDOs, but the base defaults remain fixed.
Does ISL9305IRTWCNLZ-T support forced PWM mode for noise-sensitive applications?
Yes, ISL9305IRTWCNLZ-T supports forced PWM mode for both DCD1 and DCD2 via the DCD_PARAMETER register (address 0x04h, bits B0/B1). When enabled, the converters maintain constant 3MHz switching regardless of load, eliminating frequency modulation artifacts that could interfere with RF receivers or precision analog circuits-making ISL9305IRTWCNLZ-T suitable for smartphone transceiver power domains.
How is power-good sequencing implemented on ISL9305IRTWCNLZ-T?
ISL9305IRTWCNLZ-T uses a single open-drain DCDPG pin to indicate combined status of both DCD outputs. Its assertion delay (1–200 ms) is programmable via SYS_PARAMETER register bits DCDPOR[1:0]. When both DCD1 and DCD2 are within ±3% of their nominal voltages, DCDPG releases after the programmed delay; if either rail fails, it remains low-enabling simple, reliable sequencing of downstream LDOs or system enable signals using one GPIO.
Can ISL9305IRTWCNLZ-T operate from a 2.3V input supply?
Yes, ISL9305IRTWCNLZ-T supports a minimum input voltage of 2.3V for its DCD inputs (VINDCD1/VINDCD2), as specified in Absolute Maximum Ratings and Recommended Operating Conditions (Page 5, FN7605 Rev 2.00). At this voltage, DCD1 (1.2V) and DCD2 (1.8V) remain functional with adequate headroom; however, LDO inputs must be ≥1.5V and ≤VINDCD1, so VINLDO1/VINLDO2 must be supplied from the DCD outputs or a higher auxiliary rail.
What thermal management features does ISL9305IRTWCNLZ-T include?
ISL9305IRTWCNLZ-T integrates thermal shutdown at +155°C (with +30°C hysteresis) and relies on its 4mm×4mm TQFN package with exposed E-pad for heat dissipation. Layout guidelines (Page 8) specify using ≥9 thermal vias under the E-pad connected to a solid ground plane. Thermal resistance is θJA = 40.2°C/W and θJC = 5°C/W, enabling operation up to +85°C ambient with proper PCB copper area-critical for sustained 800mA buck loading in compact handheld enclosures.
ISL9305IRTWCNLZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 16-WQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- 1.2V, 800mA
- Voltage/Current - Output 2:
- 1.8V, 800mA
- Voltage/Current - Output 3:
- 3.3V, 350mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TQFN (4x4)
ISL9305IRTWCNLZ-T FAQ
1.How can I place an order for ISL9305IRTWCNLZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL9305IRTWCNLZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL9305IRTWCNLZ-T reliable?
The price and inventory of ISL9305IRTWCNLZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL9305IRTWCNLZ-T is usually 5 days.
3.What payment methods are accepted for ISL9305IRTWCNLZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL9305IRTWCNLZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL9305IRTWCNLZ-T?
ISL9305IRTWCNLZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL9305IRTWCNLZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL9305IRTWCNLZ-T?
For technical support, including ISL9305IRTWCNLZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL9305IRTWCNLZ-T requirements.
6.How does Aetrix verify that ISL9305IRTWCNLZ-T is sourced from the original manufacturer or authorized distributors?
All ISL9305IRTWCNLZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL9305IRTWCNLZ-T meets industry standards.
7.What is the process for return or replacement of ISL9305IRTWCNLZ-T?
All ISL9305IRTWCNLZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL9305IRTWCNLZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL9305IRTWCNLZ-T part is unused and in its original packaging.
Return procedure for ISL9305IRTWCNLZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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