Renesas ISL9307IRTAAJGZ-T

Overview

ISL9307IRTAAJGZ-T from Intersil is a dual-buck + dual-LDO mini-PMIC for Li-ion/Li-polymer battery-powered systems, integrating two 1500mA synchronous step-down converters (DCD1/DCD2) and two 300mA low-input LDOs (LDO1/LDO2). It operates from 2.5–5.5V input, delivers fixed 2.8V and 2.7V LDO outputs, and uses 3MHz switching to enable compact 1.5µH inductors and low-ESR ceramic capacitors - deployed in smartphone application processors and DSP core power rails.

For engineers reviewing the ISL9307IRTAAJGZ-T datasheet, ISL9307IRTAAJGZ-T pinout, ISL9307IRTAAJGZ-T application, or ISL9307IRTAAJGZ-T equivalent, key selection criteria include its dual-buck + dual-LDO integration, 2.8V/2.7V factory-fixed LDO outputs, 3MHz PWM frequency with skip mode, thermal shutdown at 155°C, and 4mm×4mm 16-lead TQFN package with exposed thermal pad.

Technical Context

The ISL9307IRTAAJGZ-T implements peak-current-mode PWM control for both buck converters, enabling fast transient response and pulse-by-pulse current limiting up to 1500mA per channel. Its skip mode activates after 16 consecutive zero-crossing cycles under light load, reducing switching loss while maintaining regulation via internal comparator-controlled pulse bursts.

All four regulators feature independent enable pins (ENDCD1/ENDCD2/ENLDO1/ENLDO2), undervoltage lockout (2.2V on VINDCD1, 1.4V on VINLDO), and active output discharge via 115Ω internal bleeding resistors. The LDOs accept 1.5–5.5V input and deliver fixed 2.8V (LDO1) and 2.7V (LDO2) outputs with <±3% accuracy and 55dB PSRR at 1kHz.

Key Specifications

Pinout & Package

ISL9307IRTAAJGZ-T is housed in a 4mm × 4mm, 16-lead thin quad flat no-lead (TQFN) package with exposed thermal pad (JEDEC MO220K, pkg drawing L16.4X4G). The E-pad must be soldered to system ground for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-buck + dual-LDO PMIC applications.

Compared with TPS65023RSBR and RT5782AZSP, the ISL9307IRTAAJGZ-T offers exact 2.8V/2.7V factory-fixed LDO outputs with no external components, lower quiescent current in skip mode (50µA vs ≥75µA), and smaller 4mm×4mm footprint - making it optimal for space-constrained, battery-life-critical handheld designs requiring those specific LDO voltages.

Availability

ISL9307IRTAAJGZ-T is available at Aetrix Electronics and suitable for smartphone application processor core power, DSP baseband power rails, portable media player audio subsystems, and Li-ion battery-powered IoT sensor hubs requiring stable component supply across production lifecycles.

Supply support for ISL9307IRTAAJGZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Intersil Corporation is a U.S.-based designer of high-performance analog semiconductors, specializing in power management and precision signal processing for mobile, computing, and industrial markets.

The ISL9307 product line was engineered specifically for miniaturized, battery-powered consumer electronics - integrating multiple DC/DC and LDO functions into a single 4mm×4mm package to reduce PCB area, BOM count, and system-level power design complexity.

FAQ

What are the fixed output voltages of the LDOs in ISL9307IRTAAJGZ-T?

The ISL9307IRTAAJGZ-T features factory-trimmed fixed LDO outputs: LDO1 delivers 2.8V and LDO2 delivers 2.7V. These values are confirmed in the Ordering Information table on page 4 of FN7931 Rev 3.00 and require no external feedback resistors - simplifying layout and ensuring ±3% accuracy across -40°C to +85°C.

Does ISL9307IRTAAJGZ-T support power sequencing between its regulators?

Yes, ISL9307IRTAAJGZ-T supports precise power sequencing via four independent enable pins: ENDCD1, ENDCD2, ENLDO1, and ENLDO2. Each pin accepts standard CMOS logic levels (high >1.4V, low <0.4V), allowing designers to stagger startup/shutdown timing - for example, enabling LDOs before bucks to meet SoC reset timing requirements.

What package type and thermal characteristics does ISL9307IRTAAJGZ-T use?

ISL9307IRTAAJGZ-T uses a 4mm × 4mm, 16-lead TQFN package (JEDEC MO220K, drawing L16.4X4G) with an exposed thermal pad. Its typical junction-to-ambient thermal resistance (θ_JA) is 40.2°C/W when mounted on a high-thermal-conductivity test board with nine vias to solid ground plane - critical for thermal management in sealed handheld devices.

How does ISL9307IRTAAJGZ-T minimize power loss at light loads?

ISL9307IRTAAJGZ-T minimizes light-load power loss by entering skip mode: after detecting 16 consecutive zero-inductor-current cycles, it pauses switching and regulates output voltage via burst-mode pulses synchronized to the 3MHz clock. This reduces quiescent current to 50µA typical with both bucks enabled - significantly extending battery life in standby.

Can ISL9307IRTAAJGZ-T operate from a single Li-ion cell across its full discharge range?

Yes, ISL9307IRTAAJGZ-T supports input voltages from 2.5V to 5.5V, covering the full discharge curve of a single Li-ion cell (3.0V–4.2V nominal, down to ~2.8V cutoff). Its undervoltage lockout triggers at 2.2V (with 100mV hysteresis), and low-dropout operation maintains regulation even as battery voltage declines - ensuring stable 2.8V/2.7V LDO outputs throughout discharge.