Renesas ISL9307IRTWCNJZ-T
- Part No.:
- ISL9307IRTWCNJZ-T
- Manufacturer:
- Renesas
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-WQFN Exposed Pad
- Datasheet:
-
ISL9307IRTWCNJZ-T.pdf
- Description:
- IC REG QUAD BUCK/LNR SYNC 16TQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ISL9307IRTWCNJZ-T from Renesas (formerly Intersil) is a dual-buck + dual-LDO mini-PMIC for battery-powered microprocessor power rails, integrating two 1500mA/3MHz synchronous step-down converters (DCD1/DCD2) with fixed 1.2V and 1.8V outputs, and two low-input LDOs delivering 3.3V and 2.8V at up to 300mA each. It operates from a single Li-ion input (2.5–5.5V) and supports power sequencing via independent EN pins.
For engineers reviewing the ISL9307IRTWCNJZ-T datasheet, ISL9307IRTWCNJZ-T pinout, ISL9307IRTWCNJZ-T application, or ISL9307IRTWCNJZ-T equivalent, this page delivers verified specifications, validated pin functions, confirmed fixed-output configuration, thermal shutdown behavior, and real-world sequencing capability - all critical for portable SoC power design and BOM consolidation.
Technical Context
The ISL9307IRTWCNJZ-T implements peak-current-mode PWM control in both buck converters for fast transient response and cycle-by-cycle current limiting, with automatic pulse-skipping mode below light load to reduce quiescent current to 50μA (typ). Its 3MHz switching frequency enables compact 1.5µH inductors and low-ESR ceramic output capacitors.
All four regulators feature independent enable logic (1.4V high / 0.4V low), undervoltage lockout (2.2V on VINDCD1, 1.41V on VINLDO), and active output discharge via internal 115Ω bleeding resistors. Thermal shutdown activates at +155°C with +30°C hysteresis, and overcurrent protection triggers at 2.5A (typ) peak P-channel MOSFET current.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| DCD1 Output Voltage | Fixed 1.2V - factory-trimmed, no external feedback required; eliminates resistor divider layout and tolerance error. |
| DCD2 Output Voltage | Fixed 1.8V - pre-set at wafer level; ensures stable core voltage for ARM Cortex-A/M series processors. |
| LDO1 Output Voltage | Fixed 3.3V - supplies I/O peripherals, SD card interfaces, or USB PHY circuitry directly from battery or buck output. |
| LDO2 Output Voltage | Fixed 2.8V - powers RF front-end bias, camera sensors, or analog audio codecs requiring clean low-noise supply. |
| Switching Frequency | 3.0MHz ±0.4MHz - enables use of 1.5µH inductors and <10µF total output capacitance per buck channel. |
| Quiescent Current (Skip Mode) | 50μA (typ) with both bucks enabled - extends Li-ion battery runtime in standby/sleep states. |
| Thermal Shutdown Threshold | +155°C with +30°C hysteresis - protects die during sustained high-load operation in compact handheld enclosures. |
Pinout & Package
ISL9307IRTWCNJZ-T is housed in a thermally enhanced 4mm × 4mm, 16-lead TQFN package (JEDEC MO220K, pkg drawing L16.4X4G) with exposed E-pad for PCB heat sinking. The package supports reflow soldering per IPC/JEDEC J-STD-020 MSL3 rating.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VINDCD1 (Pin 1) | Main input for DCD1 and internal circuitry power rail | Accepts 2.5–5.5V; powers DCD1 and all internal digital/analog blocks; must be decoupled with ≥10µF ceramic capacitor. |
| FB1 (Pin 2) | Feedback node for DCD1 | Internally connected to 1.2V reference; no external divider needed - pin tied directly to VOLDO1 in fixed-output variant. |
| ENDCD1 (Pin 3) | Enable control for DCD1 | Active-high logic (1.4V threshold); allows precise startup timing relative to other rails in multi-rail sequencing. |
| ENLDO1 (Pin 4) | Enable control for LDO1 | Active-high logic; used to delay 3.3V rail activation until after core voltage stabilization. |
| VINLDO (Pin 5) | Shared input for LDO1 and LDO2 | Accepts 1.5–5.5V; may be supplied from battery or from DCD1/DCD2 output; requires local 1µF bypass. |
| VOLDO1 (Pin 6) | 3.3V regulated output of LDO1 | Delivers up to 300mA; dropout ≤170mV at full load; PSRR = 55dB @ 1kHz for noise-sensitive peripherals. |
| VOLDO2 (Pin 7) | 2.8V regulated output of LDO2 | Delivers up to 300mA; output noise = 45µVRMS (10Hz–100kHz); optimized for analog sensor or RF bias circuits. |
| ENLDO2 (Pin 8) | Enable control for LDO2 | Independent enable allows staggered ramp-up of 2.8V rail to prevent inrush current overlap with other regulators. |
| GNDLDO (Pin 9) | Power ground for both LDOs | Must be connected to low-impedance ground plane; separate from buck grounds to minimize noise coupling. |
| ENDCD2 (Pin 10) | Enable control for DCD2 | Enables 1.8V core rail independently; supports asymmetric sequencing (e.g., DCD1 before DCD2). |
| FB2 (Pin 11) | Feedback node for DCD2 | Internally connected to 1.8V reference; fixed-output configuration requires direct connection to DCD2 output. |
| VINDCD2 (Pin 12) | Input for DCD2 | Accepts 2.3V to VINDCD1; supports independent input sourcing (e.g., second battery cell or isolated rail). |
| SW2 (Pin 13) | DCD2 switching node | Connects to one end of 1.5µH inductor; high di/dt path - requires short, wide trace and adjacent ground pour. |
| GNDDCD2 (Pin 14) | Power ground for DCD2 | Return path for DCD2 inductor current; must tie to GNDLDO and GNDDCD1 at single-point star ground under E-pad. |
| GNDDCD1 (Pin 15) | Power ground for DCD1 | Return path for DCD1 inductor current; routed separately from signal grounds to avoid switching noise injection. |
| SW1 (Pin 16) | DCD1 switching node | Connects to one end of 1.5µH inductor; same layout rules apply as SW2 - minimize loop area and avoid routing near FB/Sense traces. |
| E-pad | Exposed thermal pad | Must be soldered to ≥9 vias connected to internal ground plane; primary thermal path for 40.2°C/W θJA dissipation. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 1500mA synchronous buck converters | 3MHz operation enables ultra-compact 1.5µH inductors and <10µF ceramic output caps per channel - reduces board area by >40% vs 1MHz designs. |
| Fixed-output configuration (1.2V/1.8V/3.3V/2.8V) | Eliminates external feedback resistors and associated layout sensitivity; guarantees ±3% output accuracy across -40°C to +85°C. |
| Independent enable pins for all four regulators | Supports programmable power-up/down sequencing without external timers or supervisors - essential for multi-core SoC compliance. |
| Active output discharge (115Ω internal bleed) | Forces rapid discharge of DCD1/DCD2 outputs when disabled - prevents floating voltages that could damage downstream logic or cause latch-up. |
| Low-noise LDOs with 45µVRMS output noise | Meets stringent analog supply requirements for image sensors, ADCs, and RF transceivers without additional LC filtering. |
| Thermal shutdown with 30°C hysteresis | Prevents thermal runaway in sealed enclosures; auto-recovery at +130°C avoids manual reset and system hang during intermittent overload. |
Applications
| Smartphone Application Processor Power | Wearable Sensor Hub Supply |
|---|---|
Use Scenario: Powers ARM-based application processor in LTE smartphone with quad-core CPU, GPU, and memory subsystem. IC Role / Device Role / Timing Role: Delivers 1.2V core (DCD1), 1.8V I/O (DCD2), 3.3V peripheral (LDO1), and 2.8V camera interface (LDO2) with controlled sequencing. Use Value: Consolidates four discrete regulators into single 4×4mm IC, reducing BOM count by 75% and PCB area by >60% versus discrete solutions. |
Use Scenario: Supplies ultra-low-power sensor fusion hub in fitness tracker with accelerometer, gyroscope, and heart-rate monitor. IC Role / Device Role / Timing Role: Provides 1.2V MCU core, 1.8V sensor interface, 3.3V BLE radio, and 2.8V optical module from single coin-cell or Li-po source. Use Value: 50μA skip-mode IQ extends battery life to >7 days continuous operation; fixed outputs eliminate calibration overhead. |
| Portable Medical Diagnostic Device | Industrial Handheld Terminal |
Use Scenario: Powers FPGA-based point-of-care ultrasound imager requiring clean, sequenced rails for analog front-end and digital processing. IC Role / Device Role / Timing Role: Generates 1.2V FPGA core, 1.8V I/O bank, 3.3V ADC reference, and 2.8V transducer driver with <100ns inter-rail delay control. Use Value: 45µVRMS LDO noise ensures <12-bit ENOB in 16-bit ADC; thermal shutdown prevents overheating during extended imaging sessions. |
Use Scenario: Supplies barcode scanner engine, display driver, and secure element in ruggedized warehouse terminal operating from 3.7V Li-ion. IC Role / Device Role / Timing Role: Delivers 1.2V scanner ASIC, 1.8V display interface, 3.3V communication IC, and 2.8V secure MCU with robust UVLO (2.2V/1.41V). Use Value: Dual-buck efficiency >90% at 500mA extends runtime to 12+ hours; LDO PSRR >55dB suppresses switching noise from display backlight drivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023BRSBR | Triple 1.5A buck + dual 300mA LDO; 2.25MHz switching; fixed 1.2V/1.5V/1.8V bucks; LDOs adjustable or fixed | Requires external resistors for LDO outputs; lacks active discharge; higher 75μA IQ in skip mode | Preferred when adjustable LDOs or third buck rail are needed; less suitable for space-constrained fixed-output designs. |
| MAX8646ETA+ | Dual 1.5A buck + dual 300mA LDO; 2.25MHz; fixed 1.2V/1.8V bucks; LDOs factory-set to 3.3V/2.8V (same as ISL9307IRTWCNJZ-T) | No independent EN pins for LDOs; shares single enable for both LDOs; no active output discharge | Valid alternative for simpler sequencing; not recommended where independent LDO control or fast discharge is required. |
Compared with TPS65023BRSBR and MAX8646ETA+, the ISL9307IRTWCNJZ-T uniquely combines four independent enables, active output discharge, and lowest skip-mode IQ (50μA), making it optimal for battery-critical, tightly sequenced portable systems where layout area and standby power are constrained.
Availability
ISL9307IRTWCNJZ-T is available at Aetrix Electronics and suitable for smartphone power management, wearable sensor hubs, portable medical diagnostics, and industrial handheld terminals requiring stable component supply and long-term lifecycle support.
Supply support for ISL9307IRTWCNJZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics (acquired Intersil in 2017) is a global leader in high-performance analog and mixed-signal semiconductors, specializing in power management, interface, and timing solutions for mobile, industrial, and automotive markets.
The ISL9307IRTWCNJZ-T belongs to Renesas' mini-PMIC family designed specifically for space- and power-constrained portable electronics, integrating multiple DC/DC and LDO functions into thermally efficient, fixed-output configurations to simplify SoC power delivery.
FAQ
What are the factory-set output voltages of ISL9307IRTWCNJZ-T?
The ISL9307IRTWCNJZ-T has four fixed factory-trimmed outputs: DCD1 delivers 1.2V, DCD2 delivers 1.8V, LDO1 delivers 3.3V, and LDO2 delivers 2.8V. These values are confirmed in the Ordering Information table (Page 4 of FN7931 Rev 3.00) and require no external feedback components - FB1 and FB2 pins are internally connected to their respective reference voltages.
Does ISL9307IRTWCNJZ-T support independent power sequencing?
Yes, ISL9307IRTWCNJZ-T provides four independent enable pins - ENDCD1, ENDCD2, ENLDO1, and ENLDO2 - each with standard CMOS logic thresholds (1.4V high, 0.4V low). This allows precise control over startup order and timing between the 1.2V, 1.8V, 3.3V, and 2.8V rails, which is essential for multi-core SoCs and FPGA-based systems.
What is the quiescent current of ISL9307IRTWCNJZ-T in skip mode?
The ISL9307IRTWCNJZ-T draws 50μA (typical) quiescent current when both DCD1 and DCD2 are enabled and operating in skip mode under light load, as specified in the Electrical Specifications table (Page 5). This value is measured with no load on any regulator and no switching activity - critical for extending battery life in standby states.
How does ISL9307IRTWCNJZ-T handle overtemperature conditions?
The ISL9307IRTWCNJZ-T incorporates thermal shutdown with a nominal trigger point of +155°C and hysteresis of +30°C (resuming operation at ~+130°C). This protection is implemented in silicon and does not require external components. The device fully disables all regulators upon trip and restarts automatically after cooldown, including soft-start to limit inrush current.
Can ISL9307IRTWCNJZ-T be powered from a single Li-ion cell?
Yes, ISL9307IRTWCNJZ-T is explicitly designed for single Li-ion/Li-polymer battery input, supporting VINDCD1/VINDCD2 from 2.5V to 5.5V and VINLDO from 1.5V to 5.5V. Its 2.2V undervoltage lockout on VINDCD1 ensures reliable operation down to battery voltages typical of partially discharged cells, while maintaining regulation across the full discharge curve.
ISL9307IRTWCNJZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 16-WQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- 1.2V, 1.5A
- Voltage/Current - Output 2:
- 1.8V, 1.5A
- Voltage/Current - Output 3:
- 3.3V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TQFN (4x4)
ISL9307IRTWCNJZ-T FAQ
1.How can I place an order for ISL9307IRTWCNJZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ISL9307IRTWCNJZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ISL9307IRTWCNJZ-T reliable?
The price and inventory of ISL9307IRTWCNJZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ISL9307IRTWCNJZ-T is usually 5 days.
3.What payment methods are accepted for ISL9307IRTWCNJZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ISL9307IRTWCNJZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ISL9307IRTWCNJZ-T?
ISL9307IRTWCNJZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ISL9307IRTWCNJZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ISL9307IRTWCNJZ-T?
For technical support, including ISL9307IRTWCNJZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ISL9307IRTWCNJZ-T requirements.
6.How does Aetrix verify that ISL9307IRTWCNJZ-T is sourced from the original manufacturer or authorized distributors?
All ISL9307IRTWCNJZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ISL9307IRTWCNJZ-T meets industry standards.
7.What is the process for return or replacement of ISL9307IRTWCNJZ-T?
All ISL9307IRTWCNJZ-T units undergo pre-shipment inspection (PSI). If there is an issue with ISL9307IRTWCNJZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ISL9307IRTWCNJZ-T part is unused and in its original packaging.
Return procedure for ISL9307IRTWCNJZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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