STMicroelectronics ISOSD61L

Overview

ISOSD61L from STMicroelectronics is a galvanically isolated second-order sigma-delta modulator with transformer-based coupling, designed for high-accuracy current/voltage sensing in high-voltage domains. It delivers 16-bit resolution (no missing codes), ±320 mV full-scale analog input range, 25 Msps 1-bit LVDS data stream output, and 5000 V_PEAK isolation voltage - deployed in solar inverters, EV chargers, and industrial motor drives.

For engineers reviewing the ISOSD61L datasheet, ISOSD61L pinout, ISOSD61L application, or ISOSD61L equivalent, key selection criteria include its 30 kV/µs CMTI, 13-bit ENOB at 25 MHz, SO-16 wide package with reinforced isolation, and LVDS/TTL dual-output compatibility for noise-immune digital interfacing in high-dV/dt environments.

Technical Context

The ISOSD61L implements a second-order sigma-delta modulator core on the high-voltage side, sampling differential analog inputs continuously at up to 25 MHz and encoding them into a 1-bit bitstream. Its embedded transformer isolation barrier separates analog input and digital output domains, enabling direct connection to shunt-based current sensing circuits without optocoupler latency or aging.

It supports both LVDS (ISOSD61L) and single-ended (ISOSD61) digital interfaces, with LVDS operation requiring matched 100 Ω termination and delivering 240–420 mV differential output swing. The modulator's output requires external SINC3 decimation filtering - typically implemented in FPGA or STM32 MCU - to reconstruct 16-bit samples at programmable output data rates.

Key Specifications

Pinout & Package

ISOSD61L uses a 16-pin SOIC wide-body (SO-16W) package with 8 mm creepage/clearance, rated for reinforced isolation. Pin 1 is marked by a beveled corner; pins 5, 6, 15 are NC (must be tied to GND in functional mode). High-voltage and low-voltage sides are physically segregated across the package centerline.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated sigma-delta modulator applications.

Compared with AMC1305M05 and AD7403, ISOSD61L uniquely combines 25 Msps LVDS streaming, 125°C operation, and 30 kV/µs CMTI - making it the only option qualified for high-reliability, high-speed current sensing in next-generation SiC-based power converters.

Availability

ISOSD61L is available at Aetrix Electronics and suitable for solar inverter design, EV onboard charger development, and industrial motor control systems requiring stable component supply across extended temperature and high-isolation reliability.

Supply support for ISOSD61L includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, analog, MEMS, and microcontrollers - with over 40 years of automotive-qualified product heritage.

The ISOSD61L belongs to ST's high-precision isolated sensing portfolio, engineered specifically for real-time current/voltage digitization in high-voltage power conversion systems demanding reinforced insulation and extreme noise immunity.

FAQ

What digital filtering is required to recover 16-bit samples from the ISOSD61L's 1-bit output?

The ISOSD61L outputs a raw 1-bit sigma-delta bitstream that must be processed by a third-order sinc (SINC3) decimation filter. This filter is commonly implemented in FPGA logic or ARM Cortex-M7/M4 MCUs (e.g., STM32H7) using fixed-point arithmetic. With a 25 MHz input clock and OSR=256, the filter yields 97.7 kSPS 16-bit samples - matching the timing and resolution specified in DS13605 Table 8.

Can ISOSD61L be used with single-ended digital interfaces, or is LVDS mandatory?

No - ISOSD61L is the LVDS-optimized variant and only supports differential MDAT± and MCLKIN± signaling. For single-ended TTL/CMOS operation, the pin-compatible ISOSD61 (non-L suffix) must be used. Attempting to drive ISOSD61L's LVDS outputs into CMOS inputs will violate voltage thresholds and cause data corruption.

How does the ISOSD61L handle common-mode transients during IGBT switching?

The ISOSD61L achieves 30 kV/µs typical common-mode transient immunity (CMTI) via its monolithic transformer isolation barrier and differential LVDS receiver design. During a 1000 V step transient with 10 ns rise time across the barrier, the internal timing circuitry maintains data validity - verified per IEC 60747-17 Annex D test conditions and confirmed in DS13605 Section 3, Table 8.

What layout practices are critical to achieve rated 5000 V_PEAK isolation performance?

To maintain rated isolation, the PCB must enforce ≥8 mm creepage and clearance between HV (pins 1–8) and LV (pins 9–16) sections - verified per IEC 60664-1. Avoid vias or traces crossing the isolation barrier; use split ground planes with no copper pour bridging the gap. Thermal relief on GNDISO/GND pins must not reduce solder joint integrity, as mechanical bond strength contributes to dielectric withstand validation.