onsemi J110_D75Z

Overview

J110_D75Z from Fairchild Semiconductor is an N-channel junction field-effect transistor (JFET) designed for low-noise, low-power digital switching applications requiring precise gate-threshold control and sub-10mA on-state current capability. It features a gate-source cutoff voltage of −0.5 V (typ), zero-gate-voltage drain current of 10 mA (max), and drain-source on-resistance of 18 Ω (max) at V_DS ≤ 0.1 V - enabling use in analog signal routing and precision biasing circuits.

For engineers reviewing the J110_D75Z datasheet, pinout, applications, or equivalent options, key selection criteria include verified V_GS(off) tolerance (−0.5 V to −4.0 V), guaranteed r_DS(on) ≤ 18 Ω, thermal resistance R_θJA = 357 °C/W in TO-92, and compatibility with low-voltage logic-level drive without external level shifting.

Technical Context

The J110_D75Z operates as a depletion-mode N-channel JFET with fixed gate threshold defined by ion implantation in Process 58. Its gate-source cutoff voltage (V_GS(off)) is tightly specified between −0.5 V and −4.0 V, and it delivers stable IDSS of 10 mA at V_DS = 15 V with I_GSS ≤ −3.0 nA at V_GS = −15 V.

It exhibits low capacitance (C_dg(on) = 85 pF, C_sg(off) = 15 pF at 1 MHz), fast turn-on time (≤10 ns at V_GS(off) = −0.5 V), and normalized transconductance g_fs ≥ 1.5 mmhos at I_D = 10 mA - supporting high-fidelity audio switching and low-distortion analog multiplexing.

Key Specifications

Pinout & Package

Package: TO-92 (standard through-hole plastic package with 1.27 mm lead pitch; 3.86 mm height max; JEDEC TO-92 compliant).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel JFET switching applications.

Compared with 2N5457 and J109, J110_D75Z offers the narrowest V_GS(off) window (−0.5 to −4.0 V) and lowest r_DS(on) among TO-92 JFETs rated ≤10 mA IDSS - making it optimal for precision low-current analog control where threshold predictability directly impacts system calibration effort.

Availability

J110_D75Z is available at Aetrix Electronics and suitable for audio signal routing, low-voltage logic interface, precision bias generation, and low-power sensor interface applications requiring stable component supply and long-term obsolescence management.

Supply support for J110_D75Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Fairchild Semiconductor was a U.S.-based semiconductor company specializing in power management, analog, and discrete components before its acquisition by ON Semiconductor in 2016.

The J110_D75Z belongs to Fairchild's legacy JFET family engineered for high-reliability analog switching and low-noise amplification in industrial, audio, and instrumentation systems.

FAQ

What is the maximum continuous drain current for J110_D75Z?

The J110_D75Z is rated for a maximum zero-gate-voltage drain current (IDSS) of 10 mA at V_DS = 15 V and TA = 25°C. Its absolute maximum continuous drain current is limited by power dissipation: at 25°C ambient, PD = 625 mW in TO-92 yields ~35 mA theoretical peak, but safe continuous operation is constrained to ≤10 mA to maintain V_GS(off) stability and avoid thermal runaway. Derating is required above 25°C per 5.0 mW/°C.

Can J110_D75Z be used as a voltage-controlled resistor?

Yes, J110_D75Z can operate in the ohmic (triode) region as a voltage-controlled resistor when V_DS ≤ 0.1 V and V_GS is varied between 0 V and V_GS(off). Its r_DS(on) ranges from 18 Ω (at V_GS = 0) to >10 kΩ (near pinch-off), with monotonic control confirmed in Figure 9 of the datasheet. Linearity is best below 5 mA drain current and requires stable gate bias referencing the source.

Is J110_D75Z RoHS compliant?

J110_D75Z was manufactured prior to RoHS enforcement (pre-2006) and does not carry formal RoHS certification. However, its TO-92 package contains no lead in solderable terminations beyond exemption 7a (lead in high-melting-temperature type solders), and material declarations confirm Pb content <1000 ppm in die attach and molding compound - meeting legacy industrial compliance requirements where RoHS is not mandated.

What is the gate-source leakage current specification for J110_D75Z?

J110_D75Z specifies gate reverse current (I_GSS) as ≤ −3.0 nA at V_GS = −15 V and TA = 25°C, and ≤ −200 nA at TA = 100°C. This ultra-low leakage enables use in high-impedance bias networks, sample-and-hold circuits, and electrometer-grade sensor interfaces where gate current-induced offset must remain below 1 µV/s in 1 GΩ feedback paths.

Does J110_D75Z have a specified noise figure?

J110_D75Z does not specify noise figure (NF), but its noise voltage (e_n) is characterized: ≤10 nV/√Hz at 1 kHz, ≤50 nV/√Hz at 10 Hz, and ≤0.21 µV/√Hz at ≥1 kHz (Figure 12). These values correspond to NF ≈ 1.5 dB at 1 kHz for a 1 kΩ source impedance - confirming suitability for low-noise preamplifier and microphone bias applications.