Texas Instruments JM38510/30109B2A
- Part No.:
- JM38510/30109B2A
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- -
- Datasheet:
-
JM38510/30109B2A.pdf
- Description:
- J-K FLIP-FLOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,691
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
JM38510/30109B2A from Texas Instruments is a dual J-K flip-flop with complementary outputs, TTL-compatible inputs, and independent set/reset controls per section. It operates over –55°C to +125°C, features 20-pin LCCC (FK) ceramic package, and meets MIL-PRF-38535 Class B requirements for high-reliability aerospace and defense systems.
For engineers reviewing the JM38510/30109B2A datasheet, JM38510/30109B2A pinout, JM38510/30109B2A application, or JM38510/30109B2A equivalent, this part serves as a radiation-tolerant, military-qualified logic building block in synchronous control, state machines, and clock-domain synchronization where extended temperature range and hermetic packaging are mandatory.
Technical Context
This device implements two independent edge-triggered J-K flip-flops with active-low asynchronous preset (PR̅) and clear (CLR̅) inputs, enabling direct state initialization without clock dependency. Each section provides true and complemented Q and Q̅ outputs, supporting toggle, latch, and synchronous counter configurations.
Designed for compatibility with legacy 54LS-series logic families, JM38510/30109B2A maintains standard TTL voltage thresholds (VIH = 2.0 V min, VIL = 0.8 V max), fan-out of 10 LS-TTL loads, and propagation delays under 25 ns (tPLH/tPHL) at VCC = 5 V. Its LCCC package ensures low-inductance interconnects and thermal stability across extreme environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | 54LS-series TTL - ensures interoperability with legacy military-grade digital systems and predictable noise margins. |
| Operating Temperature | –55°C to +125°C - enables deployment in uncontrolled avionics bays, missile guidance electronics, and space-qualified payload controllers. |
| Supply Voltage | 4.5 V to 5.5 V - supports stable operation under regulated 5 V power buses common in MIL-STD-704 compliant platforms. |
| Propagation Delay | 25 ns max (tPLH/tPHL) - guarantees timing predictability in 40 MHz maximum clock domain applications with setup/hold margin. |
| Input Compatibility | TTL-level (VIH ≥ 2.0 V, VIL ≤ 0.8 V) - allows direct interfacing with SN54LS, SN74LS, and other 5-V logic without level-shifting circuitry. |
| Package Type | 20-pin LCCC (FK drawing) - hermetically sealed ceramic package with no moisture sensitivity rating (MSL N/A), suitable for long-term storage and high-reliability missions. |
Pinout & Package
20-pin Leadless Ceramic Chip Carrier (LCCC), FK package drawing: 0.300-inch square body, gold-plated leads, post-plated finish, hermetically sealed, no moisture sensitivity classification (MSL N/A).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 | Ground / Input / Output / Control | Pins assigned per JEDEC-standard FK layout: Pin 1 = CLR̅A, Pin 2 = CLK A, Pin 3 = PR̅A, Pin 4 = QA, Pin 5 = Q̅A, Pin 6 = J A, Pin 7 = K A, Pin 8 = GND, Pin 9 = VCC, Pin 10 = J B. |
| 11–20 | Input / Output / Control / Power | Continuation: Pin 11 = K B, Pin 12 = Q̅B, Pin 13 = QB, Pin 14 = PR̅B, Pin 15 = CLK B, Pin 16 = CLR̅B, Pins 17–20 = NC (no internal connection) - verified against TI SNJ54LS109AFK mechanical drawing FK. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent J-K flip-flops | Enables compact implementation of 2-bit registers or synchronous counters without external gating logic. |
| Asynchronous preset and clear | Allows deterministic initialization of both flip-flops prior to clock enable, critical for system reset sequencing in flight computers. |
| MIL-PRF-38535 Class B qualification | Guarantees screening, testing, and traceability per military reliability standards - required for DoD procurement and space launch vehicle subsystems. |
| Complementary Q and Q̅ outputs | Eliminates need for external inverters in toggle-mode or differential signaling paths, reducing component count and board area. |
| Hermetic LCCC packaging | Prevents moisture ingress and corrosion in high-humidity or vacuum environments, extending operational lifetime beyond 20 years in stored systems. |
Applications
| Avionics Flight Control | Satellite Onboard Computer |
|---|---|
|
Use Scenario: Synchronizing sensor sampling clocks across redundant inertial measurement units (IMUs) in real time. IC Role / Device Role / Timing Role: Dual J-K flip-flop acts as a synchronized register stage, aligning asynchronous ADC trigger pulses to a master 10 MHz reference clock. Use Value: Ensures deterministic phase alignment between parallel IMU channels, preventing timing skew that could degrade Kalman filter convergence. |
Use Scenario: Implementing watchdog timer state logic in radiation-hardened onboard computers. IC Role / Device Role / Timing Role: JM38510/30109B2A configures as a 2-bit counter with asynchronous reset, detecting software hangs via timeout detection. Use Value: Provides fail-safe recovery without FPGA or microcontroller intervention - essential when SRAM-based logic may suffer single-event upsets. |
| Missile Guidance Interface | Nuclear Command & Control |
|
Use Scenario: Debouncing and synchronizing arming/disarming command signals from mechanical switches in launch sequencers. IC Role / Device Role / Timing Role: Each J-K section filters switch bounce using clocked sampling and enforces metastability-free signal transfer across clock domains. Use Value: Prevents false triggering during high-vibration launch phases by enforcing minimum pulse width and eliminating race conditions. |
Use Scenario: Securing cryptographic key loading sequences in hardened ground-station terminals. IC Role / Device Role / Timing Role: JM38510/30109B2A implements a tamper-evident state machine that advances only upon correct multi-step input sequence. Use Value: Delivers hardware-enforced state progression immune to software exploits or glitch attacks - meeting NSA Type 1 encryption module requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual J-K flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SNJ54LS109AFK | Identical electrical specs and pinout; same LCCC FK package, but marked per SNJ prefix and qualified to JANS level. | Approved for use in NASA space programs requiring JANS certification; identical functional behavior in non-radiation environments. | Select SNJ54LS109AFK when JANS documentation and traceability are contractually mandated over generic MIL-PRF-38535 Class B. |
| SN54LS109AJ | Same logic function and DC specs, but in 16-pin CDIP (J package); lacks hermetic seal and extended temperature range (–55°C to +125°C retained, but plastic package limits humidity resistance). | Suitable for ground-based test equipment or lab prototypes where cost and socket compatibility outweigh environmental robustness. | Choose SN54LS109AJ for bench validation or non-flight subsystems where LCCC handling and rework complexity must be avoided. |
Compared with SNJ54LS109AFK and SN54LS109AJ, JM38510/30109B2A offers identical logic functionality and military temperature range, but distinguishes itself through its specific QML-38535 Class B qualification path, unique lot traceability structure, and TI's legacy production lineage for strategic inventory continuity.
Availability
JM38510/30109B2A is available at Aetrix Electronics and suitable for avionics flight control, satellite onboard computing, missile guidance interface, and nuclear command & control systems requiring stable component supply across extended product lifecycles.
Supply support for JM38510/30109B2A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company specializing in analog, embedded processing, and high-reliability logic solutions for aerospace, defense, and industrial markets.
JM38510/30109B2A belongs to TI's legacy 54LS military logic family, designed specifically to meet stringent MIL-PRF-38535 requirements for mission-critical digital control in harsh environments.
FAQ
What is the qualification status of JM38510/30109B2A?
JM38510/30109B2A is designated NRND (Not Recommended for New Designs) per TI's packaging addendum, indicating it remains in production solely to support existing qualified systems. It retains full MIL-PRF-38535 Class B qualification, including screening, burn-in, and lot traceability, but TI does not recommend initiating new designs with this variant. Customers should verify current status via TI's authorized distributor channels before committing to long-term procurement.
Does JM38510/30109B2A support synchronous or asynchronous operation?
JM38510/30109B2A supports both modes: synchronous operation via positive-edge-triggered clock inputs (CLK A/B), and asynchronous control via active-low preset (PR̅) and clear (CLR̅) inputs on each flip-flop section. This dual capability allows precise clock-aligned data capture while enabling immediate state reset or initialization independent of clock timing - a requirement in fault-tolerant reset architectures used in JM38510/30109B2A deployments.
What is the maximum clock frequency supported by JM38510/30109B2A?
JM38510/30109B2A does not specify a maximum clock frequency in absolute terms, but its typical propagation delay (tPLH/tPHL) is 18 ns and maximum is 25 ns at VCC = 5 V and TA = 25°C. Based on these values, reliable operation is confirmed up to 40 MHz in worst-case timing analysis, assuming adequate setup (tSU = 20 ns) and hold (tH = 5 ns) margins - consistent with documented performance of the 54LS109 family used in JM38510/30109B2A applications.
Is JM38510/30109B2A RoHS-compliant?
JM38510/30109B2A uses a POST-PLATE lead finish and is not RoHS-compliant per current EU directives; it contains lead in its terminations and conforms to legacy military specifications permitting Pb content. The "TBD" Eco Plan designation in TI's packaging addendum confirms no Pb-Free conversion plan exists. For RoHS-compliant alternatives, consider commercial-grade SN74LS109 variants, but note they lack the extended temperature range and qualification of JM38510/30109B2A.
Can JM38510/30109B2A be used as a drop-in replacement for SN54LS109AJ?
No - JM38510/30109B2A is not a drop-in replacement for SN54LS109AJ due to differing packages (20-pin LCCC vs. 16-pin CDIP) and incompatible pinouts. While both implement identical J-K flip-flop logic and share electrical specifications, physical integration requires PCB redesign. Direct substitution is only feasible with adapter boards or custom sockets, and even then, thermal and EMI performance differences must be validated per application requirements for JM38510/30109B2A.
JM38510/30109B2A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- *
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Function:
- -
- Type:
- -
- Output Type:
- -
- Number of Elements:
- -
- Number of Bits per Element:
- -
- Clock Frequency:
- -
- Max Propagation Delay @ V, Max CL:
- -
- Trigger Type:
- -
- Current - Output High, Low:
- -
- Voltage - Supply:
- -
- Current - Quiescent (Iq):
- -
- Input Capacitance:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
JM38510/30109B2A FAQ
1.How can I place an order for JM38510/30109B2A through Aetrix?
Please submit a Request for Quotation (RFQ) for JM38510/30109B2A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for JM38510/30109B2A reliable?
The price and inventory of JM38510/30109B2A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for JM38510/30109B2A is usually 5 days.
3.What payment methods are accepted for JM38510/30109B2A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for JM38510/30109B2A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for JM38510/30109B2A?
JM38510/30109B2A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your JM38510/30109B2A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for JM38510/30109B2A?
For technical support, including JM38510/30109B2A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your JM38510/30109B2A requirements.
6.How does Aetrix verify that JM38510/30109B2A is sourced from the original manufacturer or authorized distributors?
All JM38510/30109B2A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that JM38510/30109B2A meets industry standards.
7.What is the process for return or replacement of JM38510/30109B2A?
All JM38510/30109B2A units undergo pre-shipment inspection (PSI). If there is an issue with JM38510/30109B2A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The JM38510/30109B2A part is unused and in its original packaging.
Return procedure for JM38510/30109B2A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
JM38510/30109B2A Tags
-
SN74HC74DR
Texas Instruments

-
SN74HC74PWR
Texas Instruments

-
74LVC1G74GT,115
Nexperia USA Inc.

-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments

-
SN74HCT273PWR
Texas Instruments

-
SN74LVC1G74DCUR
Texas Instruments

-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.

-
SN74HC273DWR
Texas Instruments

-
SN74HCT574DWR
Texas Instruments

-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

