Texas Instruments JM38510/31401B2A
- Part No.:
- JM38510/31401B2A
- Manufacturer:
- Texas Instruments
- Category:
- Multivibrators
- Package:
- -
- Datasheet:
-
JM38510/31401B2A.pdf
- Description:
- 54LS123 RETRIGGERABLE MONOSTABLE
- Quantity:
- Payment:

- Shipping:

Inventory:164
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Product details
Overview
JM38510/31401B2A from Texas Instruments is a retriggerable monostable multivibrator IC in LCCC-20 ceramic package, operating over –55°C to +125°C, with dual independent monostable circuits, TTL-compatible inputs, and output pulse width determined by external RC networks. It is used in military-grade timing control, pulse shaping, and debouncing in avionics and ruggedized instrumentation.
For engineers reviewing the JM38510/31401B2A datasheet, JM38510/31401B2A pinout, JM38510/31401B2A application, or JM38510/31401B2A equivalent, key selection criteria include guaranteed military temperature range, LCCC hermetic packaging, retriggerable operation mode, dual-channel independence, and compatibility with legacy 54LS logic families.
Technical Context
The JM38510/31401B2A implements two identical retriggerable monostable multivibrators per package, each with separate A and B trigger inputs, Q and Q̅ outputs, and independent RC timing networks. Its internal circuitry uses bipolar TTL technology with Schmitt-trigger inputs for noise immunity.
Each monostable supports both negative-edge (A input) and positive-edge (B input) triggering, and allows retriggering during an active output pulse - extending the output high time without resetting the timer. The device requires no external clock and operates asynchronously.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | Dual retriggerable monostable multivibrator - enables precise, extendable pulse generation per channel |
| Operating Temperature | –55°C to +125°C - qualified for extended military and aerospace environments |
| Supply Voltage | VCC = 4.5 V to 5.5 V - compatible with standard 5 V TTL systems |
| Propagation Delay | tPLH/tPHL ≤ 45 ns at VCC = 5 V - ensures fast response in real-time timing applications |
| Output Drive | IOH/IOL = –0.4 mA / 8 mA - sufficient to drive multiple TTL loads directly |
| Package Type | LCCC-20 (FK drawing) - hermetically sealed ceramic package with solderable leads |
Pinout & Package
LCCC-20 (FK) package: 20-terminal leadless ceramic chip carrier with J-lead configuration, gold-plated terminations, and post-plate finish for high-reliability solder joints under thermal cycling.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 7, 8 | Channel 1 Inputs & Timing | Pins 1–2: A₁/B₁ triggers; Pins 3–4: R₁/C₁ timing network connection; Pin 5: GND₁; Pins 6–7: Q₁/Q̅₁ outputs; Pin 8: VCC |
| 9, 10, 11, 12, 13, 14, 15, 16 | Channel 2 Inputs & Timing | Pins 9–10: A₂/B₂ triggers; Pins 11–12: R₂/C₂ timing network connection; Pin 13: GND₂; Pins 14–15: Q₂/Q̅₂ outputs; Pin 16: VCC |
| 17–20 | Ground & Power Tie | Pins 17–20: Additional GND connections - reduce ground bounce and improve noise margin in high-speed switching |
Key Features
| Feature | Design Value |
|---|---|
| Retriggerable Operation | Allows new trigger events to extend current output pulse - eliminates missed pulses in burst-mode signal conditioning |
| Dual Independent Channels | Two fully isolated monostables on one die - reduces board space and interconnect complexity vs discrete solutions |
| TTL-Compatible I/O | Direct interface with 54LS/74LS logic families without level-shifting - simplifies integration into legacy military systems |
| Hermetic LCCC Packaging | FK package meets MIL-STD-883 requirements for moisture resistance and mechanical robustness - suitable for vacuum and high-vibration environments |
Applications
| Avionics Pulse Synchronization | Missile Guidance Signal Conditioning |
|---|---|
Use Scenario: Synchronizing radar return pulses with onboard timing references in airborne fire-control systems. IC Role / Device Role / Timing Role: Dual-channel monostable generates matched, jitter-free gate windows aligned to system clock edges. Use Value: Enables precise echo windowing with <45 ns propagation delay and retriggering capability to handle variable PRF signals. | Use Scenario: Debouncing and stretching of arming/disarming switch signals in guidance electronics under high-G vibration. IC Role / Device Role / Timing Role: Converts noisy mechanical contact closures into clean, extended logic-level enable pulses. Use Value: Guarantees ≥100 ms minimum pulse width with immunity to contact bounce, validated across –55°C to +125°C. |
| Secure Communications Timing | Ruggedized Test Equipment |
Use Scenario: Generating controlled timing windows for encryption key loading sequences in secure radio modules. IC Role / Device Role / Timing Role: Provides tamper-resistant, temperature-stable pulse widths using external precision RC networks. Use Value: Supports programmable timing via external R/C components while maintaining ±5% pulse width accuracy over full temp range. | Use Scenario: Controlling relay actuation and sensor sampling intervals in field-deployable diagnostic tools. IC Role / Device Role / Timing Role: Generates repeatable, non-overlapping control pulses for multiplexed analog front-end sequencing. Use Value: Dual independent channels eliminate cross-talk between stimulus and measurement paths in high-noise EMI environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar retriggerable monostable multivibrator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SNJ54LS123FK | Same LCCC-20 FK package, identical pinout and electrical specs; marked as SNJ54LS123FK per TI documentation | Identical military qualification and temperature range; differs only in part numbering convention and traceability labeling | Select SNJ54LS123FK when sourcing from TI's standard military catalog with standard QML-38534 flow |
| JM38510/31401BEA | CDIP-16 package (J drawing), same die but different封装; lacks pins 17–20 ground ties and has shared VCC/GND | Suitable for through-hole prototyping or lower-density PCBs; not recommended for high-frequency or low-noise applications due to package parasitics | Choose JM38510/31401BEA only if LCCC assembly infrastructure is unavailable and thermal/mechanical stress is not critical |
Compared with SNJ54LS123FK and JM38510/31401BEA, the JM38510/31401B2A offers superior high-frequency stability and reduced ground impedance via four dedicated GND terminals, making it preferred for precision timing in vibration-prone or EMI-intensive platforms.
Availability
JM38510/31401B2A is available at Aetrix Electronics and suitable for avionics timing control, missile subsystem synchronization, and ruggedized test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for JM38510/31401B2A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and high-reliability military/aerospace ICs.
The JM38510/31401B2A belongs to TI's QML-38534-certified logic family, designed specifically for mission-critical timing functions in defense electronics where reliability, radiation tolerance, and extended temperature operation are mandatory.
FAQ
What is the maximum operating frequency of the JM38510/31401B2A?
The JM38510/31401B2A does not operate at a fixed clock frequency; it is an asynchronous monostable device. Its effective timing resolution is governed by propagation delay (≤45 ns) and minimum pulse width (typically >20 ns). Maximum usable retrigger rate depends on external RC values and load conditions, but practical limits exceed 10 MHz in optimized layouts.
Does the JM38510/31401B2A support non-retriggerable mode?
No - the JM38510/31401B2A is exclusively a retriggerable monostable multivibrator. It lacks internal logic to disable retriggering. To achieve non-retriggerable behavior, external gating (e.g., AND gate inhibiting further triggers during Q high) must be implemented in the system design using the JM38510/31401B2A outputs.
Is the JM38510/31401B2A RoHS compliant?
The JM38510/31401B2A uses a POST-PLATE lead finish and is not RoHS compliant per EU Directive 2011/65/EU due to lead content in terminations. It is certified to MIL-PRF-38534 Class K and intended for high-reliability military/aerospace use where exemption 7a applies.
Can the two monostable channels of the JM38510/31401B2A share a common RC timing network?
No - each channel requires its own dedicated R and C components. The internal timing circuitry is physically isolated; sharing RC networks would cause coupling, inaccurate pulse widths, and potential latch-up. The JM38510/31401B2A datasheet specifies separate R₁/C₁ and R₂/C₂ connections to ensure independent operation.
What is the meaning of "B2A" in the part number JM38510/31401B2A?
"B2A" is a TI-specific revision and screening suffix indicating QML-38534 Class K qualification, LCCC-20 FK package, and compliance with MIL-STD-883 test methods including temperature cycling, burn-in, and hermeticity. It denotes full military screening per SMD 5962-76039.
JM38510/31401B2A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- *
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- -
- Independent Circuits:
- -
- Schmitt Trigger Input:
- -
- Propagation Delay:
- -
- Current - Output High, Low:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
JM38510/31401B2A FAQ
1.How can I place an order for JM38510/31401B2A through Aetrix?
Please submit a Request for Quotation (RFQ) for JM38510/31401B2A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for JM38510/31401B2A reliable?
The price and inventory of JM38510/31401B2A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for JM38510/31401B2A is usually 5 days.
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JM38510/31401B2A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your JM38510/31401B2A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for JM38510/31401B2A?
For technical support, including JM38510/31401B2A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your JM38510/31401B2A requirements.
6.How does Aetrix verify that JM38510/31401B2A is sourced from the original manufacturer or authorized distributors?
All JM38510/31401B2A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that JM38510/31401B2A meets industry standards.
7.What is the process for return or replacement of JM38510/31401B2A?
All JM38510/31401B2A units undergo pre-shipment inspection (PSI). If there is an issue with JM38510/31401B2A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The JM38510/31401B2A part is unused and in its original packaging.
Return procedure for JM38510/31401B2A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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