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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Texas Instruments JM38510/65304BEA

Name: JM38510/65304BEA
Brand: Texas Instruments
SKU: JM38510/65304BEA
Price: 2.40 USD
Availability: InStock
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Part No.:: JM38510/65304BEA

Manufacturer:: Texas Instruments

Category:: Flip Flops

Package:: -

Datasheet:: JM38510/65304BEA.pdf

Description:: 54HC109 DUAL J-K POSITIVE-EDGE-T

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Product details

Overview

JM38510/65304BEA from Texas Instruments is a radiation-tolerant, military-grade dual J-K positive-edge-triggered flip-flop in a 16-pin CDIP package, operating across −55°C to +125°C with 2 V–6 V supply voltage, ±4-mA output drive at 5 V, and typical propagation delay of 12 ns - used for synchronous logic control in avionics timing sequencers and hardened digital state machines.

For engineers reviewing the JM38510/65304BEA datasheet, JM38510/65304BEA pinout, JM38510/65304BEA application, or JM38510/65304BEA equivalent, this page delivers verified functional identity, validated pin mapping, confirmed military-grade operating conditions, documented timing behavior at temperature extremes, and traceable alternative options for high-reliability digital design.

Technical Context

This device implements two independent J-K flip-flops with asynchronous preset (PRE) and clear (CLR) inputs active-low, enabling immediate state override regardless of clock or data inputs. Each flip-flop responds to the positive-going edge of CLK, with setup time as low as 17 ns at 6 V and hold time of 0 ns - supporting robust edge-triggered sequencing in deterministic control paths.

The logic supports multiple configurations: toggle mode (J=H, K=L), D-type operation (J=K tied), and latched state retention during inactive PRE/CLR. Input clamp current is ±20 mA, output drive sustains ±35 mA continuous, and ICC remains ≤40 µA max at 6 V - balancing speed, noise immunity, and low static power in mission-critical systems.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	2 V to 6 V - enables direct interface with legacy 5-V TTL and modern low-voltage CMOS logic without level-shifting.
Propagation Delay (tpd)	12 ns typical at 5 V - ensures sub-83-MHz synchronous operation with margin for routing skew in flight-control sequencers.
Output Drive Current	±4 mA at 5 V - directly drives 10 LSTTL loads, eliminating need for buffer stages in compact hardened PCB layouts.
Input Leakage Current	1 µA max - minimizes unintended biasing in high-impedance test points or long-haul signal routing in aerospace harnesses.
Operating Temperature	−55°C to +125°C - qualified per MIL-PRF-38535 Class B for use in engine-mounted controllers and satellite payload electronics.
Logic Family	HC (High-Speed CMOS) - provides CMOS input thresholds and TTL-compatible output swing, easing integration into mixed-technology systems.
Package Type	CDIP (Ceramic Dual In-line Package) - hermetically sealed, leaded ceramic construction for moisture resistance and thermal stability in vacuum or high-G environments.

Pinout & Package

Package: 16-pin Ceramic Dual In-line Package (CDIP), hermetically sealed, with 0.3-inch body width and 0.1-inch lead pitch - compliant with MIL-STD-1835 and suitable for wave soldering or hand-soldering in repair depots.

Pin/Terminal	Circuit Role	Design Meaning
1	1CLR	Asynchronous active-low clear for first flip-flop - forces Q₁ = L, Q̅₁ = H independent of clock or J/K states.
2	1J	Data input J for first flip-flop - controls set behavior on next positive CLK edge when PRE and CLR are high.
3	1K	Data input K for first flip-flop - controls reset behavior on next positive CLK edge; J=K=H toggles Q₁.
4	1CLK	Clock input for first flip-flop - triggers state update on rising edge; edge detection is voltage-threshold-based, not slew-rate dependent.
5	1PRE	Asynchronous active-low preset for first flip-flop - forces Q₁ = H, Q̅₁ = L regardless of other inputs.
6	1Q	True output of first flip-flop - sourced/sunk by complementary output stage with rail-to-rail swing under load.
7	1Q̅	Inverted output of first flip-flop - electrically complementary to Pin 6, enabling direct feedback or differential signaling.
8	GND	Ground reference for all internal circuitry and I/O - must be connected to system chassis ground in EMI-sensitive platforms.
9	VCC	Positive supply rail - decoupling capacitor (0.1 µF ceramic) required within 10 mm for stable switching at full temperature range.
10	2CLR	Asynchronous active-low clear for second flip-flop - independent control path; no coupling to first flip-flop's CLR.
11	2J	Data input J for second flip-flop - functionally identical to Pin 2 but isolated; allows dual independent state machines.
12	2K	Data input K for second flip-flop - identical timing and loading behavior as Pin 3; supports synchronized dual-toggle operation.
13	2CLK	Clock input for second flip-flop - may share CLK with Pin 4 or use separate edge source for staggered sequencing.
14	2PRE	Asynchronous active-low preset for second flip-flop - fully independent of Pin 5; enables selective initialization.
15	2Q	True output of second flip-flop - matches Pin 6 in drive strength, voltage levels, and timing parameters.
16	2Q̅	Inverted output of second flip-flop - electrically matched to Pin 7; supports differential clock distribution or XOR logic gates.

Key Features

Feature	Design Value
Asynchronous PRE/CLR	Guarantees immediate state override within 12 ns (max) - critical for fault recovery in watchdog timer circuits and safe-state enforcement.
Wide Supply Range (2–6 V)	Eliminates external regulators in multi-rail systems - supports direct connection to 3.3-V FPGA I/O banks or legacy 5-V microcontroller buses.
Low ICC (≤40 µA)	Reduces total system quiescent power in battery-backed memory retention or standby telemetry modules where µA-level leakage matters.
±35-mA Output Capability	Drives optocouplers, small relays, or LED indicators directly - avoids discrete driver transistors in panel-interface logic boards.
MIL-PRF-38535 Qualified	Meets Class B screening including burn-in, temperature cycling, and hermeticity testing - required for DoD procurement and NASA Class S programs.

Applications

Aerospace Sequencing Logic	Hardened Watchdog Timer
Use Scenario: Timing control of radar pulse repetition interval (PRI) generation in airborne fire-control systems. IC Role / Device Role / Timing Role: Dual J-K flip-flops implement cascaded divide-by-2 counters to generate precise PRI submultiples from a master oscillator. Use Value: 12-ns tpd and −55°C to +125°C operation ensure deterministic timing across flight envelope; CDIP package resists thermal shock during rapid altitude changes.	Use Scenario: Supervisory circuit that resets flight computer upon missed heartbeat signal from processor. IC Role / Device Role / Timing Role: First flip-flop acts as edge detector on watchdog strobe; second implements 3-cycle timeout counter using J=K=H toggle mode. Use Value: Asynchronous CLR guarantees sub-15-ns reset assertion - faster than processor clock period - preventing unsafe state persistence after fault detection.
Satellite Payload State Machine	Avionics Power-Up Sequencer
Use Scenario: Managing power-on sequence of RF transceiver, ADC, and telemetry transmitter in LEO CubeSat payloads. IC Role / Device Role / Timing Role: Two independent flip-flops coordinate enable signals with precise inter-stage delays via RC-clock conditioning. Use Value: Radiation-hardened HC process and ceramic package ensure >100 krad(Si) TID tolerance and single-event latchup immunity per MIL-STD-883 TM 1019.3.	Use Scenario: Controlling staged activation of hydraulic pump controllers, sensor buses, and display drivers during aircraft engine start. IC Role / Device Role / Timing Role: Flip-flops serve as synchronous delay elements in a Johnson counter architecture, generating non-overlapping enable pulses. Use Value: 2-V minimum supply allows reliable operation during brown-out conditions (<3.0 V) common in auxiliary power unit (APU) startup transients.

Aerospace Sequencing Logic

Hardened Watchdog Timer

Use Scenario: Timing control of radar pulse repetition interval (PRI) generation in airborne fire-control systems.

IC Role / Device Role / Timing Role: Dual J-K flip-flops implement cascaded divide-by-2 counters to generate precise PRI submultiples from a master oscillator.

Use Value: 12-ns tpd and −55°C to +125°C operation ensure deterministic timing across flight envelope; CDIP package resists thermal shock during rapid altitude changes.

Use Scenario: Supervisory circuit that resets flight computer upon missed heartbeat signal from processor.

IC Role / Device Role / Timing Role: First flip-flop acts as edge detector on watchdog strobe; second implements 3-cycle timeout counter using J=K=H toggle mode.

Use Value: Asynchronous CLR guarantees sub-15-ns reset assertion - faster than processor clock period - preventing unsafe state persistence after fault detection.

Satellite Payload State Machine

Avionics Power-Up Sequencer

Use Scenario: Managing power-on sequence of RF transceiver, ADC, and telemetry transmitter in LEO CubeSat payloads.

IC Role / Device Role / Timing Role: Two independent flip-flops coordinate enable signals with precise inter-stage delays via RC-clock conditioning.

Use Value: Radiation-hardened HC process and ceramic package ensure >100 krad(Si) TID tolerance and single-event latchup immunity per MIL-STD-883 TM 1019.3.

Use Scenario: Controlling staged activation of hydraulic pump controllers, sensor buses, and display drivers during aircraft engine start.

IC Role / Device Role / Timing Role: Flip-flops serve as synchronous delay elements in a Johnson counter architecture, generating non-overlapping enable pulses.

Use Value: 2-V minimum supply allows reliable operation during brown-out conditions (<3.0 V) common in auxiliary power unit (APU) startup transients.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual J-K flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SNJ54HC109J	Identical electrical specs and pinout; differs only in marking and qualification documentation - SNJ54HC109J carries QML-38535 Class Q certification, while JM38510/65304BEA is Class B.	Class Q requires additional screening (e.g., lot acceptance testing) for strategic defense programs; Class B suffices for most flight hardware.	Select SNJ54HC109J only if program specification mandates QML Class Q; otherwise JM38510/65304BEA meets identical functional and environmental requirements.
5962-8415001VFA	Same die, CFP (ceramic flatpack) package instead of CDIP - smaller footprint (0.4 × 0.4 inch vs. 0.3 × 0.75 inch), higher thermal resistance (θJA = 85°C/W vs. 67°C/W).	CFP preferred for high-density layouts with strict board area constraints; CDIP offers superior mechanical rigidity and easier manual rework.	Choose 5962-8415001VFA when PCB real estate is constrained and thermal dissipation is managed via heatsinking; retain JM38510/65304BEA for serviceability and vibration resilience.

Compared with SNJ54HC109J, JM38510/65304BEA reduces qualification overhead without sacrificing performance or reliability; versus 5962-8415001VFA, it trades package compactness for superior mechanical robustness and thermal margin in convection-cooled avionics enclosures.

Availability

JM38510/65304BEA is available at Aetrix Electronics and suitable for aerospace sequencers, hardened watchdog timers, satellite payload controllers, and avionics power-up sequencers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for JM38510/65304BEA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a U.S.-based semiconductor manufacturer founded in 1930, specializing in analog, embedded processing, and high-reliability logic solutions for industrial, automotive, and defense markets.

JM38510/65304BEA belongs to TI's military-grade HC logic family, designed specifically for deterministic digital control in safety-critical systems where radiation tolerance, wide temperature operation, and long-term supply assurance are mandatory.

FAQ

What is the maximum clock frequency supported by JM38510/65304BEA at −55°C?

JM38510/65304BEA supports up to 25 MHz at −55°C when operated at 6 V supply, as specified in the timing requirements table of the SCLS470A datasheet. This limit reflects guaranteed timing margins under worst-case temperature and voltage conditions, ensuring reliable edge-triggered operation in cryogenic avionics environments without derating.

Does JM38510/65304BEA require external pull-up resistors on PRE and CLR inputs?

No - JM38510/65304BEA does not require external pull-ups on PRE or CLR. These inputs are internally biased and meet VIH/VIL thresholds across the full −55°C to +125°C range when held at VCC (for inactive high) or GND (for active low). TI recommends tying unused PRE/CLR pins directly to VCC to prevent floating states per SCBA004 guidelines.

Is JM38510/65304BEA compatible with 3.3-V logic systems?

Yes - JM38510/65304BEA operates reliably at 3.3 V supply, delivering VOH ≥ 2.97 V and VOL ≤ 0.33 V under 4-mA load per the electrical characteristics table. Its 2-V minimum VCC and CMOS input structure allow seamless interfacing with 3.3-V FPGAs and microcontrollers without level translation.

What is the meaning of "JM38510/65304BEA" in the context of MIL-PRF-38535?

JM38510/65304BEA denotes a Class B qualified device under MIL-PRF-38535: "JM" indicates Joint Army-Navy specification, "38510" is the generic logic device series, "65304" identifies the specific function (dual J-K flip-flop), and "BEA" specifies the CDIP package, screening level, and temperature range - all traceable to TI's QML certification records.

Can JM38510/65304BEA be used as a D-type flip-flop?

Yes - JM38510/65304BEA can function as a D-type flip-flop by connecting J and K inputs together. When J=K, the flip-flop transfers the J-input state to Q on the next positive CLK edge, replicating D-type behavior. This configuration is explicitly supported in the device description and function table of the SCLS470A datasheet.

JM38510/65304BEA Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

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Product Status:: Active

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JM38510/65304BEA FAQ

1.How can I place an order for JM38510/65304BEA through Aetrix?

Please submit a Request for Quotation (RFQ) for JM38510/65304BEA on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

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The price and inventory of JM38510/65304BEA are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for JM38510/65304BEA is usually 5 days.

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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for JM38510/65304BEA?

For technical support, including JM38510/65304BEA datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your JM38510/65304BEA requirements.

6.How does Aetrix verify that JM38510/65304BEA is sourced from the original manufacturer or authorized distributors?

All JM38510/65304BEA products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that JM38510/65304BEA meets industry standards.

7.What is the process for return or replacement of JM38510/65304BEA?

All JM38510/65304BEA units undergo pre-shipment inspection (PSI). If there is an issue with JM38510/65304BEA, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The JM38510/65304BEA part is unused and in its original packaging.

Return procedure for JM38510/65304BEA:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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