NXP Semiconductors JN5174/001Y
- Part No.:
- JN5174/001Y
- Manufacturer:
- NXP Semiconductors
- Category:
- RF Transceiver ICs
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
JN5174/001Y.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 40HVQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
JN5174/001Y from NXP Semiconductors is an IEEE 802.15.4-compliant wireless microcontroller integrating ARM Cortex-M3 CPU, 2.4 GHz transceiver, 160 kB Flash, 32 kB RAM, and 4 kB EEPROM. It delivers −96 dBm receiver sensitivity, +10 dBm configurable transmit power, and ultra-low 12.7 mA receive current-enabling multi-year coin-cell operation in ZigBee 3.0 and Thread smart lighting nodes.
For engineers reviewing the JN5174/001Y datasheet, JN5174/001Y pinout, JN5174/001Y application, or JN5174/001Y equivalent, key selection considerations include OTA firmware upgradability, integrated 128-bit AES security coprocessor, antenna diversity support, and dual UART/I²C/SPI peripheral set for sensor-actuator interfacing in battery-constrained IoT endpoints.
Technical Context
The JN5174/001Y implements a unified memory architecture with ARM Cortex-M3 core running at programmable clock speeds (1–32 MHz), tightly coupled to IEEE 802.15.4 MAC accelerator and hardware AES-CCM security engine. Its radio subsystem includes integrated PA, temperature-compensated crystal oscillator, and automatic RX antenna diversity based on energy detection.
Power management integrates six low-power modes-including deep sleep at 100 nA-and dedicated 32 kHz sleep timers, while analog peripherals feature 6-channel 10-bit ADC with autonomous sampling, internal temperature/battery sensors, and fail-safe I²C supporting open-drain DIO4/DIO5 pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | ARM Cortex-M3 CPU with Thumb-2 instruction set, debug via SWD/JTAG, 32 MHz max clock |
| Memory | 160 kB embedded Flash (boot + application), 32 kB RAM, 4 kB EEPROM with 100 k write endurance |
| Radio | 2.4 GHz IEEE 802.15.4 PHY/MAC compliant; −96 dBm sensitivity; +10 dBm TX power; 106 dB link budget |
| Power | 12.7 mA RX current; 0.6 µA sleep timer mode; 100 nA deep sleep with external wake-up |
| Analog | 6-input 10-bit ADC with internal temp/battery sensing; programmable analog comparator; VREF/ADC1 shared pin |
| Peripherals | 2×UART (one with RTS/CTS), I²C master/slave (fail-safe, open-drain DIO4/DIO5), SPI master/slave (2 select outputs), 8 timers (6×PWM) |
| Security | Dedicated 128-bit AES-CCM coprocessor supporting MIC-32/-64/-128, ENC, ENC-MIC modes per IEEE 802.15.4-2006 |
Pinout & Package
Package: HVQFN40, 6 × 6 mm, 0.5 mm pitch, lead-free/RoHS compliant, exposed paddle (VSSA) for thermal dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DIO0–DIO15, DIO17–DIO18 | Digital I/O (multiplexed) | 18 general-purpose bidirectional pins; configurable as ADC inputs (DIO0–DIO3), PWM outputs (DIO12–DIO14), or UART/I²C/SPI functions |
| RF_IO | RF antenna interface | Single-ended 50 Ω RF port requiring external matching network; supports antenna diversity control via ADO/ADE signals |
| XTAL_IN / XTAL_OUT | 32 MHz crystal oscillator | Drives system clock generator; requires external 32 MHz crystal and load capacitors to analog ground |
| VDDA / VDDD / VB_DIG / VB_RF1 / VB_RF2 / VB_SYNTH / VB_VCO | Power supply domains | Separate analog/digital/RF/regulator supplies; each requires dedicated 100 nF decoupling; VB_RF1/VB_RF2 tied together |
| RESET_N | Active-low reset input | Pulled up internally; assertion resets CPU, peripherals, and memory; compatible with push-button or supervisor IC |
Key Features
| Feature | Design Value |
|---|---|
| OTA firmware update | Full stack and application code upgrade over-the-air without external Flash-reduces BOM and enables field maintenance |
| Antenna diversity | Auto-RX switching between two antennas based on real-time energy detection-improves link robustness in multipath environments |
| Fail-safe I²C interface | Open-drain DIO4/DIO5 with built-in glitch filter and pull-up control-prevents bus lockup during noise or hot-plug events |
| Ultra-low-power sleep timer | 0.6 µA operation with 32 kHz RC or crystal source-enables precise wake-up scheduling for periodic sensor polling |
| Integrated security accelerator | Hardware AES-CCM engine offloads encryption/authentication from CPU-ensures deterministic timing for secure frame processing |
| Battery monitoring | On-chip voltage monitor with 8 programmable thresholds plus ADC-based battery sensing-supports state-of-charge estimation in coin-cell systems |
Applications
| Smart Lighting Control Node | ZigBee 3.0 Thermostat Sensor |
|---|---|
Use Scenario: Wireless LED driver node receiving dimming commands and reporting status in residential lighting mesh. IC Role / Device Role / Timing Role: Primary wireless MCU executing ZigBee Light Link stack, managing PWM dimming output, and sampling ambient light via ADC. Use Value: 12.7 mA RX current and 100 nA deep sleep enable >10-year CR2032 operation; OTA updates allow remote firmware patching without hardware access. | Use Scenario: Battery-powered room thermostat transmitting temperature/humidity data every 5 minutes to gateway. IC Role / Device Role / Timing Role: IEEE 802.15.4 endpoint running ZCL cluster library, using internal temp sensor and 6-channel ADC for external humidity sensor interface. Use Value: Integrated temperature sensor and battery monitor eliminate discrete components; −96 dBm sensitivity ensures reliable reception in thermally insulated wall cavities. |
| Thread Border Router Endpoint | Energy-Harvesting Light Switch |
Use Scenario: Low-power edge node bridging BLE commissioning to Thread network in smart home hub architecture. IC Role / Device Role / Timing Role: Dual-PAN ID capable MCU handling Thread network layer, MAC acceleration, and secure TLS handshake via AES coprocessor. Use Value: Hardware MAC accelerator reduces CPU load during high-throughput beacon processing; 106 dB link budget extends range to detached garages or sheds. | Use Scenario: Self-powered wall switch harvesting mechanical energy to trigger light control without batteries or wiring. IC Role / Device Role / Timing Role: Ultra-low-leakage wake-up controller sampling piezoelectric pulse, then launching full ZigBee stack only on valid press event. Use Value: 100 nA deep sleep minimizes quiescent drain; internal comparators detect microsecond-level switch transients-eliminating external wake-up circuitry. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar wireless microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| EM3581-RTR | 8051 core, 256 kB Flash, no integrated AES accelerator, 13.5 mA RX current | Lacks hardware security coprocessor; requires software AES implementation increasing latency and flash footprint | Choose when legacy EmberZNet stack compatibility is required and security performance is secondary |
| CC2652R1F | ARM Cortex-M4F core, 352 kB Flash, Bluetooth 5.1 + IEEE 802.15.4 dual-mode, 5.9 mA RX current | Supports concurrent BLE/Thread operation but requires external Flash for full ZigBee 3.0 stack | Prefer for multi-protocol gateways where BLE provisioning coexists with Thread mesh routing |
Compared with EM3581-RTR and CC2652R1F, the JN5174/001Y provides best-in-class balance of ultra-low RX current, integrated AES security, and single-chip ZigBee/Thread stack execution-making it optimal for cost-sensitive, long-life smart lighting endpoints where power and security are non-negotiable.
Availability
JN5174/001Y is available at Aetrix Electronics and suitable for smart lighting controls, ZigBee 3.0 sensor networks, and Thread-based home automation requiring stable component supply across multi-year production cycles.
Supply support for JN5174/001Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets.
The JN517x product line was designed specifically for ultra-low-power, standards-compliant wireless mesh networking in battery-operated smart home and commercial lighting applications-emphasizing OTA upgradability, integrated security, and minimal external component count.
FAQ
What wireless protocols does the JN5174/001Y natively support?
The JN5174/001Y natively supports IEEE 802.15.4 PHY/MAC layer operation and is qualified for ZigBee PRO, ZigBee 3.0, and Thread protocol stacks. Its hardware MAC accelerator and AES coprocessor are optimized for these standards, enabling full-stack execution in its 160 kB Flash without external memory. NXP-provided software libraries abstract lower-layer complexity, allowing direct application development on JN5174/001Y.
Does the JN5174/001Y require external Flash memory for ZigBee 3.0 operation?
No, the JN5174/001Y does not require external Flash memory for ZigBee 3.0 operation. Its 160 kB embedded Flash accommodates both the ZigBee 3.0 stack and user application code, and supports Over-The-Air (OTA) firmware updates. This eliminates external memory components, reduces PCB area, and simplifies certification-key advantages confirmed in NXP's JN517x reference designs and ZigBee certification reports for JN5174/001Y.
How many digital I/O pins does the JN5174/001Y provide, and what are their key electrical characteristics?
The JN5174/001Y provides 18 digital I/O pins (DIO0–DIO15, DIO17–DIO18), all configurable as inputs or outputs with programmable internal pull-up/pull-down resistors (~50 kΩ). DIO4 and DIO5 support true open-drain I²C operation with built-in glitch filtering. All DIO pins tolerate voltages up to 0.3 V above VDDA, and six (DIO0–DIO3, DIO17–DIO18) double as analog inputs for the 10-bit ADC or comparator-subject to pull-up disablement per NXP's pin configuration guidelines for JN5174/001Y.
What is the minimum supply voltage for the JN5174/001Y, and how does it impact radio performance?
The JN5174/001Y operates from 2.0 V to 3.6 V. At the minimum 2.0 V supply, radio performance remains fully specified: receiver sensitivity stays at −96 dBm, and maximum transmit power is reduced to +8.5 dBm (19.6 mA) versus +10 dBm (22.5 mA) at 3.3 V. The device maintains full functionality-including AES acceleration, ADC operation, and sleep modes-across this range, enabling direct coin-cell (2.0–3.0 V) use without regulators, as validated in NXP's JN5174/001Y battery lifetime characterization data.
Can the JN5174/001Y support antenna diversity, and how is it implemented?
Yes, the JN5174/001Y supports antenna diversity with automatic receive switching (Auto RX). It uses dedicated ADO (antenna diversity odd) and ADE (antenna diversity even) output pins to control external RF switches, while continuously monitoring received signal energy on both paths. The baseband controller selects the antenna with higher energy in real time-improving link reliability in multipath environments. This function is hardware-accelerated and requires no CPU intervention, as documented in Section 4.1 and Figure 2 of the JN5174/001Y datasheet.
JN5174/001Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- JN517X
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4
- Protocol:
- Zigbee®
- Modulation:
- -
- Frequency:
- 2.4GHz ~ 2.485GHz
- Data Rate (Max):
- -
- Power - Output:
- 10dBm
- Sensitivity:
- -96.5dBm
- Memory Size:
- 160kB Flash, 4kB EEPROM, 32kB RAM
- Serial Interfaces:
- I2C, PWM, SPI, UART
- GPIO:
- 1
- Voltage - Supply:
- 2V ~ 3.6V
- Current - Receiving:
- 12.7mA ~ 14.8mA
- Current - Transmitting:
- 14mA ~ 22.5mA
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 40-HVQFN (6x6)
JN5174/001Y FAQ
1.How can I place an order for JN5174/001Y through Aetrix?
Please submit a Request for Quotation (RFQ) for JN5174/001Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for JN5174/001Y reliable?
The price and inventory of JN5174/001Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for JN5174/001Y is usually 5 days.
3.What payment methods are accepted for JN5174/001Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for JN5174/001Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for JN5174/001Y?
JN5174/001Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your JN5174/001Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for JN5174/001Y?
For technical support, including JN5174/001Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your JN5174/001Y requirements.
6.How does Aetrix verify that JN5174/001Y is sourced from the original manufacturer or authorized distributors?
All JN5174/001Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that JN5174/001Y meets industry standards.
7.What is the process for return or replacement of JN5174/001Y?
All JN5174/001Y units undergo pre-shipment inspection (PSI). If there is an issue with JN5174/001Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The JN5174/001Y part is unused and in its original packaging.
Return procedure for JN5174/001Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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