STMicroelectronics L5989D

Overview

L5989D from STMicroelectronics is a monolithic synchronous step-down DC-DC switching regulator delivering 4 A continuous output current (5 A pulsed), operating from 2.9 V to 18 V input, with programmable 100–1000 kHz switching frequency, 0.6 V to VIN adjustable output voltage, and integrated high-side PMOS/low-side NMOS power switches in HTSSOP16 package. It serves as primary voltage regulator in LCD TV power rails and industrial DC-DC modules.

For engineers reviewing the L5989D datasheet, L5989D pinout, L5989D application, or L5989D equivalent, key selection criteria include its 200 ns minimum on-time, voltage-mode control architecture, programmable UVLO thresholds for 3.3 V/5 V/12 V buses, MLCC-compatible operation, and pre-bias startup capability for stable cold-start in consumer electronics power supplies.

Technical Context

The L5989D implements a voltage-mode control loop using a sawtooth oscillator and error amplifier comparison, enabling stable regulation at ultra-low duty cycles (e.g., 0.6 VOUT from 18 VIN) without current-sense dependency. Its BCD6 process delivers 50 mΩ typical high-side PMOS and 67 mΩ typical low-side NMOS R_DS(on), supporting high efficiency across wide input/output ratios.

Core protection logic includes dual-switch current limiting (3.6–4.4 A high-side peak, 4.14–5.06 A low-side valley), latched/non-latched OVP selectable via U/O/S pin, thermal shutdown at 150 °C, and UVLO with hysteresis (200 mV for 3.3 V bus, 1 V for 12 V bus). The multifunction U/O/S pin configures three independent features-UVLO threshold, OVP latch mode, and sink enable-using discrete voltage levels.

Key Specifications

Pinout & Package

Package: HTSSOP16 with exposed thermal pad (R_thJA = 40 °C/W), lead pitch 0.65 mm, body size 5 mm × 4.4 mm × 1.2 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck regulator applications.

Compared with MP2315DJ-LF-Z and TPS54560BQDDARQ1, the L5989D uniquely combines 4 A capability, 2.9 V low-input operation, programmable UVLO/OVP/sink, and pre-bias startup in a single HTSSOP16 package-making it optimal for consumer and industrial applications demanding flexibility, compactness, and cold-start robustness without automotive qualification overhead.

Availability

L5989D is available at Aetrix Electronics and suitable for LCD TV power rails, industrial DC-DC modules, car radio audio supplies, and networking router core voltage generation requiring stable component supply across long production lifecycles.

Supply support for L5989D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The L5989D belongs to ST's monolithic synchronous buck regulator product line, engineered for high integration, wide input range, and flexible configuration in space-constrained power management applications.

FAQ

What is the minimum input voltage required for L5989D to regulate a 0.6 V output?

The L5989D requires a minimum input voltage of 2.9 V to maintain regulation at 0.6 V output, verified across temperature and load conditions per Table 2 and Section 4 of the datasheet. This 2.9 V lower limit is enforced by internal bias circuitry and remains valid even at maximum 4 A load and 125 °C junction temperature.

How does the U/O/S pin configure UVLO, OVP latch, and sink functions simultaneously?

The U/O/S pin uses three distinct voltage thresholds (0–0.2 V, 0.26–0.65 V, 0.71–1.525 V) to encode combinations of UVLO bus (3.3 V or 12 V), OVP latch mode (latched or not), and sink enable (enabled or disabled). Each combination corresponds to a specific resistor divider from VREF to GND, as defined in Tables TH1–TH8 and Section 5.1.

Can L5989D operate with zero output load while maintaining regulation?

Yes, the L5989D supports zero-load operation with 35 μA total standby quiescent current. Its voltage-mode control loop and error amplifier remain active, holding output voltage within ±1% regulation (0.595–0.605 V at FB) even with no load, as specified in Table 4 under "DC characteristic" and confirmed in Figure 39 (soft-start) and Figure 36 (load regulation).

What is the purpose of separate SGND and PGND pins, and how should they be routed?

SGND carries low-current analog signals (error amp, reference, feedback) while PGND handles high di/dt power return currents. They must be connected at a single point near the IC's exposed thermal pad to prevent noise coupling from power loops into the control circuitry-this layout is validated in Figures 23–24 and Section 6.7 of the datasheet.