STMicroelectronics L6382DTR

Overview

L6382D from STMicroelectronics is a high-voltage BCD-based power management unit and gate driver IC for LED drivers with PFC + half-bridge topology. It integrates four MOSFET drivers (PFC, high-side/low-side half-bridge, auxiliary), 3.3 V ±1% reference (30 mA), internal bootstrap diode, two-point VCC regulation, digital overcurrent protection output (CSO), and cross-conduction interlock - enabling single-chip control of dimmable/non-dimmable offline LED drivers up to 150 W.

For engineers reviewing the L6382D datasheet, L6382D pinout, L6382D application, or L6382D equivalent, key selection considerations include its 400 kHz digital input capability, integrated HV startup (0–600 V), 120 mA/250 mA sink-source drive strength per channel, UVLO thresholds (VCCON = 14 V typ., VCCOFF = 8.25 V), and SO-20 package compatibility with thermal resistance R_thJA = 120 °C/W.

Technical Context

The L6382D implements a state-machine–driven power management architecture with three operational modes: startup (HV generator active, VREF disabled), save mode (HVSU cycled ON/OFF to regulate VCC between 12.75–14.85 V, VREF limited to 10 mA), and operating mode (TPR enabled, OCP active, full 30 mA VREF, drivers enabled after 10 µs delay and HGI falling edge). All logic inputs (PFI, LSI, HSI, HEI) are TTL-compatible (0.8 V low / 2.2 V high) and support up to 400 kHz switching.

Its patented synchronous bootstrap structure replaces external diodes by integrating a 150 Ω on-resistance bootstrap switch with 2.4 V forward drop at 10 mA, while the two-point regulator (TPR) uses LGI-edge–triggered PSW switching to maintain VCC between 12.45–13.48 V in operating mode - eliminating need for external charge pump circuitry.

Key Specifications

Pinout & Package

Package: SO-20 (Small Outline, 20-pin, surface-mount), 1.27 mm pitch, body size 12.8 × 7.5 mm, R_thJA = 120 °C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LED driver controller applications.

Compared with IRS2505LTRPBF and UCC28064ADR, the L6382D uniquely combines PFC + half-bridge gate driving, 3.3 V MCU supply, and autonomous multi-mode power management in one SO-20 IC - reducing total solution size by ≥30% and eliminating six external components typically needed for discrete implementations.

Availability

L6382D is available at Aetrix Electronics and suitable for dimmable LED street lighting, non-dimmable LED panel drivers, and smart LED retrofit lamps requiring stable component supply, long-lifecycle assurance, and industrial-grade reliability.

Supply support for L6382D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for automotive, industrial, and consumer markets.

The L6382D belongs to ST's LED Driver Controller product line, engineered specifically for cost-sensitive, high-reliability offline LED lighting systems requiring integrated PFC, half-bridge control, and autonomous power management - targeting 30–150 W applications with simplified design and reduced bill-of-materials.

FAQ

What is the maximum allowable voltage on the HVSU pin, and how does it behave during startup?

The HVSU pin accepts up to 600 V DC. During startup, the internal 600 V MOS transistor draws ~10 mA to charge the VCC bypass capacitor. Once VCC reaches 14 V (typ.), the HVSU generator shuts off. If VCC drops below 8.25 V later, it re-enables to sustain operation - ensuring reliable cold-start under varying line conditions without external HV resistors.

How does the L6382D implement cross-conduction protection between high-side and low-side drivers?

The L6382D uses hardware-level interlocking: when either LSG or HSG is active, the other driver is forcibly disabled for the duration of the active pulse plus a fixed blanking interval. This prevents simultaneous conduction in the half-bridge leg - eliminating shoot-through risk without relying on MCU timing margins or external logic.

Can the VREF output power a typical 3.3 V ARM Cortex-M0 microcontroller during full operation?

Yes. The VREF pin delivers 3.3 V ±1% with up to 30 mA continuous current in operating mode - sufficient for most Cortex-M0 MCUs (e.g., STM32G030, NXP LPC802) drawing ≤25 mA at 48 MHz. A 0.22 µF film capacitor between VREF and GND is mandatory to suppress noise and maintain regulation stability under dynamic load.

What happens to the drivers during an overcurrent event detected on the CSI pin?

When CSI exceeds 0.56 V, the internal comparator triggers immediately: CSO latches high (TTL level), and both LSG and HSG outputs are forced low within 200 ns. The PFG and HEG drivers remain unaffected unless separately disabled by MCU logic. Recovery requires cycling VCC below UVLO or asserting LGI = HGI = low simultaneously - ensuring fail-safe shutdown without MCU intervention.