STMicroelectronics L6561

Overview

L6561 from STMicroelectronics is a transition-mode Power Factor Correction (PFC) controller IC designed for AC-DC front-end stages in electronic lamp ballasts, SMPS, and adapters. It features 1% precision internal reference voltage (2.5 V @ 25°C), ±400 mA totem-pole gate driver output, and micro-power start-up current (50 µA typ.), enabling high-efficiency operation across 85–265 VAC input ranges with <4% THD in wide-range configurations.

For engineers reviewing the L6561 datasheet, L6561 pinout, L6561 application, or L6561 equivalent, this device is selected for PFC stage design requiring precise overvoltage protection (±7% threshold accuracy), zero-current detection-based timing control, low-quiescent-current standby operation (<2.1 mA), and direct MOSFET/IGBT drive without external buffers.

Technical Context

The L6561 implements a mixed-signal BCD process architecture integrating a precision error amplifier, analog multiplier, current-sense comparator with on-chip filtering, and zero-current detector (ZCD) with disable functionality. Its transition-mode (critical conduction mode) control eliminates need for slope compensation and enables fixed-frequency-like behavior with inherent soft-switching benefits.

Operation relies on ZCD pin monitoring of inductor current zero-crossing to trigger switching cycles, while the multiplier stage combines rectified line voltage (via MULT pin) and error amplifier output (COMP) to generate duty-cycle-modulated gate drive. The internal 2.5 V reference sets output voltage regulation via resistive divider at INV pin, and dynamic/static OVP protection activates at 35–45 µA sensed current through the feedback network.

Key Specifications

Pinout & Package

Available in DIP-8 and SO-8 packages per Table 1; both share identical pin mapping and thermal performance (R_{th j-amb} = 100°C/W for SO-8, 150°C/W for DIP-8).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PFC controller applications.

Compared with UCC3817 and FAN7530, the L6561 uniquely integrates ZCD-based disable, on-chip current-sense filtering, and dual-stage OVP-making it optimal for compact, low-THD, universal-input PFC stages where board space and component count are constrained.

Availability

L6561 is available at Aetrix Electronics and suitable for electronic lamp ballasts, AC-DC adapters, and industrial SMPS requiring stable component supply, long-term lifecycle support, and consistent parametric performance across temperature and input voltage variations.

Supply support for L6561 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, and microcontroller solutions for industrial, automotive, and consumer markets.

The L6561 belongs to ST's legacy PFC controller product line, engineered specifically for transition-mode AC-DC conversion in lighting and adapter applications demanding high power factor, low THD, and minimal external component count.

FAQ

What is the recommended minimum value for the current-sense resistor (R_s) when using L6561 with a 10 A peak inductor current?

The L6561's CS pin has a 1.7 V typical current-sense reference clamp. To avoid saturation, R_s must satisfy V_CS = I_peak × R_s ≤ 1.7 V. For 10 A peak, R_s ≤ 170 mΩ. A standard 150 mΩ, 1 W metal-film resistor provides 1.5 V drop and sufficient margin against overvoltage during transients.

Can the L6561 operate without an external compensation network between COMP and INV pins?

No. The COMP-to-INV compensation network (typically a series RC) is mandatory to stabilize the error amplifier loop. Omitting it causes oscillation or uncontrolled output voltage drift. ST recommends a 1 nF capacitor in series with a 10 kΩ resistor for standard 80 W ballast designs, as verified in EVAL6561-80 schematics.

How does the ZCD pin disable function interact with the internal start-up timer?

When ZCD is grounded, the L6561 enters low-current standby (I_q ≈ 1.4 mA) and halts switching. Releasing ZCD to float or pull above 250 mV re-enables the internal 70–400 µs start-up timer, which then initiates normal soft-start sequence-ensuring controlled re-entry into regulation without inrush stress.

Is the L6561 compatible with MOSFETs having gate charge (Q_g) exceeding 50 nC?

Yes-the ±400 mA totem-pole driver supports Q_g up to ~70 nC at 70 kHz switching frequency. For a 60 nC MOSFET, t_rise ≈ Q_g/I_source = 60 nC / 400 mA = 150 ns, well within the 100 ns max specified for 1 nF load. Layout-dependent parasitics remain the limiting factor, not driver capability.